TDA4VM21 datasheet(157/331 Pages) TI

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overshoot

undershoot

period

Overshoot = 20% of nominal

IO supply voltage

Undershoot = 20% of nominal

IO supply voltage

Tovershoot + Tundershoot < 20% of Tperiod

Figure 6-1. IO Transient Voltage Ranges

6.2 ESD Ratings

VALUE

UNIT

V(ESD)

Electrostatic discharge

Human-body model (HBM), per AEC Q100-002, Revision J(1)

±1000

Charged-device model (CDM), per AEC Q100-011,

Revision J

All pins

±250

Corner pins (A1,

AJ29)

±750

(1)

AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.

6.3 Power-On-Hour (POH) Limits

IP(1) (2) (3) VOLTAGE DOMAIN

VOLTAGE (V)

(MAX)

FREQUENCY

(MHz) (MAX)

Tj(°C)

POH

All

100%

All

All Supported OPPs

Automotive -40°C to 125°C

(4)

20000

All

100%

All

All Supported OPPs

Extended -40°C to 105°C

100000

All

100%

All

All Supported OPPs

Commercial 0°C to 90°C

100000

(1)

This information is provided solely for your convenience and does not extend or modify the warranty provided under TI's standard

terms and conditions for TI semiconductor products.

(2)

Unless specified in the table above, all voltage domains and operating conditions are supported in the device at the noted

temperatures

(3)

POH is a function of voltage, temperature and time. Usage at higher voltages and temperatures will result in a reduction in POH.

(4)

Automotive profile is defined as 20000 power on hours with junction temperature as follows: 5%@-40°C, 65%@70°C, 20%@110°C,

and 10%@125°C.

6.4 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)

SUPPLY NAME

DESCRIPTION

MIN

(1)

NOM

MAX

(1)

UNIT

VDD_CORE

Boot/Active voltage for MAIN domain core supply

0.76

0.8

0.84

VDD_MCU

Boot/Active voltage for MCUSS core supply

0.76

0.8

0.89

VDD_CPU

Boot voltage for CPU core supply, applied at cold

power up event

0.76

0.8

0.84

Active voltage for CPU core supply, after AVS mode

enabled in software

AVS

(4)-5%

AVS

(4)

AVS

(4)+5%

VDD_CPU AVS Range

AVS valid voltage range for VDD_CPU

0.6

0.9

VDDA_0P8_DLL_MMC0

MMC PLL analog supply

0.76

0.8

0.84

VDDAR_CORE

Main domain RAM supply

0.81

0.85

0.89

VDDAR_MCU

MCUSS RAM supply

0.81

0.85

0.89

VDDAR_CPU

CPU RAM supply

0.81

0.85

0.89

VDDA_0P8_DP

Displayport SERDES clock supply

0.76

0.8

0.84

VDDA_0P8_DP_C

Displayport SERDES clock supply

0.76

0.8

0.84

VDDA_0P8_DSITX

DSITX clock supply

0.76

0.8

0.84

www.ti.com

TDA4VM-Q1, TDA4VM

SPRSP36K – SEPTEMBER 2021 – REVISED APRIL 2024

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