TDA4VM21 datasheet(181/331 Pages) TI

181 / 331 page

J7ES_ELCH_03

Valid Configuration

VDDSHV0_MCU, VDDSHV1_MCU, VDDSHV2_MCU

(3)(5a)

VDDSHV0, VDDSHV1, VDDSHV2, VDDSHV3,

VDDSHV4, VDDSHV5, VDDSHV6

,VDDA_3P3_USB

(3)(5b)

VDDS_MMC0

VDDA_MCU_PLLGRP0, VDDA_MCU_TEMP, VDDA_ADC0,

VDDA_ADC1, VDDA_POR_WKUP, VDDA_WKUP

VDD_MCU, VDDAR_MCU

(7)

VDDA_0P8_SERDES0_1,

VDDA_0P8_SERDES2_3, VDDA_0P8_SERDES_C0_1,

VDDA_0P8_SERDES_C2_3, VDDA_0P8_DP, VDDA_0P8_DP_C,

VDDA_0P8_CSIRX, VDDA_0P8_UFS, VDDA_0P8_USB,

VDDA_0P8_DSITX, VDDA_0P8_DSITX_C

VDD_CORE, VDD_MCU,

VDDAR_CORE,

VDDAR_MCU

VDDAR_CPU,

(7)

MCU_PORz

(9)(10)

PORz

(9)(10)

OSC1_XI, OSC1_XO

WKUP_LFOSC0_XI, WKUP_LFOSC0_XO

(optional)

WKUP_OSC0_XI, WKUP_OSC0_XO

(optional)

VDDS_DDR, VDDS_DDR_C, VDDS_DDR_BIAS

VDDSHV0_MCU, VDDSHV1_MCU, VDDSHV2_MCU

(4)

VDDSHV0, VDDSHV1, VDDSHV2, VDDSHV3,

VDDSHV4, VDDSHV5, VDDSHV6

(4)

VDDS_OSC1, VDDA_PLLGRP0,

VDDA_PLLGRP1, VDDA_PLLGRP2,

VDDA_PLLGRP3, VDDA_PLLGRP4, VDDA_PLLGRP5,

VDDA_PLLGRP6, VDDA_TEMP0_1, VDDA_TEMP2_3,

VDD_CPU

VDDA_1P8_CSIRX, VDDA_1P8_UFS, VDDA_1P8_USB,

VDDA_1P8_DP, VDDA_1P8_DSITX, VDDA_1P8_MLB,

VDDA_1P8_SERDES0_1, VDDA_1P8_SERDES2_3

(6)

VDDA_0P8_PLL_DDR, VDDA_0P8_DLL_MMC0, VDDA_0P8_PLL_MLB

SYSBOOT[17:0]

(9)

Active

Entry into MCU only

MCU only

Exit from MCU only

Figure 6-7. Entry and Exit of MCU Only Sequencing

6.9.2.7 Entry and Exit of DDR Retention State

Entry into DDR Retention (Suspend-to-RAM or S2R) state is accomplished by executing a power down

sequence except for the 1 device DDR supply group (VDDS_DDR_BIAS, VDDS_DDR, and VDDS_DDR_C

at 1.1V), and 1 additional discrete SDRAM supply (VDD_LPDDR4_1V8 at 1.8V; not shown in diagram below)

that remain energized. Exit from DDR Retention state is accomplished by executing a power up sequence with

these 2 DDR supply groups remaining energized throughout the sequence. The example diagram shown is for

an Isolated MCU & Main PDN type with eMMC support.

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TDA4VM-Q1, TDA4VM

SPRSP36K – SEPTEMBER 2021 – REVISED APRIL 2024

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