TDA4VM21 datasheet(237/331 Pages) TI

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6.9.5.12.2.2 GPMC and NOR Flash Switching Characteristics – Asynchronous Mode

NO.

PARAMETER

DESCRIPTION

MODE

(15)

MIN

MAX

UNIT

133 MHz

(16)

FA0

tw(be[x]nV)

Pulse duration, output lower-byte enable and

command latch enable GPMC_BE0n_CLE, output

upper-byte enable GPMC_BE1n valid time

Read

N(12)

Write

N(12)

FA1

tw(csnV)

Pulse duration, output chip select GPMC_CSn[i](13)

low

Read

A(1)

Write

A(1)

FA3

td(csnV-advnIV)

Delay time, output chip select GPMC_CSn[i](13)

valid to output address valid and address latch

enable GPMC_ADVn_ALE invalid

Read

B(2)-2.55 B(2)+2.65

Write

B(2)-2.55 B(2)+2.65

FA4

td(csnV-oenIV)

Delay time, output chip select GPMC_CSn[i](13)

valid to output enable GPMC_OEn_REn invalid

(Single read)

div_by_1_mode;

C(3)-2.55 C(3)+2.65

FA9

td(aV-csnV)

Delay time, output address GPMC_A[27:1] valid to

output chip select GPMC_CSn[i](13) valid

div_by_1_mode;

J(9)-2.55 J(9)+2.65

FA10 td(be[x]nV-csnV)

Delay time, output lower-byte enable and

command latch enable GPMC_BE0n_CLE, output

upper-byte enable GPMC_BE1n valid to output

chip select GPMC_CSn[i](13) valid

div_by_1_mode;

J(9)-2.55 J(9)+2.65

FA12 td(csnV-advnV)

Delay time, output chip select GPMC_CSn[i](13)

valid to output address valid and address latch

enable GPMC_ADVn_ALE valid

div_by_1_mode;

K(10)-2.55

(10)+2.65

FA13 td(csnV-oenV)

Delay time, output chip select GPMC_CSn[i](13)

valid to output enable GPMC_OEn_REn valid

div_by_1_mode;

L(11)-2.55 L(11)+2.65

FA16 tw(aIV)

Pulse duration output address GPMC_A[26:1]

invalid between 2 successive read and write

accesses

div_by_1_mode;

G(7)

FA18 td(csnV-oenIV)

Delay time, output chip select GPMC_CSn[i](13)

valid to output enable GPMC_OEn_REn invalid

(Burst read)

div_by_1_mode;

I(8)-2.55

I(8)+2.65

FA20 tw(aV)

Pulse duration, output address GPMC_A[27:1]

valid - 2nd, 3rd, and 4th accesses

div_by_1_mode;

D(4)

FA25 td(csnV-wenV)

Delay time, output chip select GPMC_CSn[i](13)

valid to output write enable GPMC_WEn valid

div_by_1_mode;

E(5)-2.55 E(5)+2.65

FA27 td(csnV-wenIV)

Delay time, output chip select GPMC_CSn[i](13)

valid to output write enable GPMC_WEn invalid

div_by_1_mode;

F(6)-2.55 F(6)+2.65

FA28 td(wenV-dV)

Delay time, output write enable GPMC_WEn valid

to output data GPMC_AD[15:0] valid

div_by_1_mode;

2.65

FA29 td(dV-csnV)

Delay time, output data GPMC_AD[15:0] valid to

output chip select GPMC_CSn[i](13) valid

div_by_1_mode;

J(9)-2.55 J(9)+2.65

FA37 td(oenV-aIV)

Delay time, output enable GPMC_OEn_REn valid

to output address GPMC_AD[15:0] phase end

div_by_1_mode;

2.65

(1)

For single read: A = (CSRdOffTime - CSOnTime) × (TimeParaGranularity + 1) × GPMC_FCLK(14)

For single write: A = (CSWrOffTime - CSOnTime) × (TimeParaGranularity + 1) × GPMC_FCLK(14)

For burst read: A = (CSRdOffTime - CSOnTime + (n - 1) × PageBurstAccessTime) × (TimeParaGranularity + 1) × GPMC_FCLK(14)

For burst write: A = (CSWrOffTime - CSOnTime + (n - 1) × PageBurstAccessTime) × (TimeParaGranularity + 1) × GPMC_FCLK(14)

with n being the page burst access number

(2)

For reading: B = ((ADVRdOffTime - CSOnTime) × (TimeParaGranularity + 1) + 0.5 × (ADVExtraDelay - CSExtraDelay)) ×

GPMC_FCLK(14)

For writing: B = ((ADVWrOffTime - CSOnTime) × (TimeParaGranularity + 1) + 0.5 × (ADVExtraDelay - CSExtraDelay)) ×

GPMC_FCLK(14)

(3)

C = ((OEOffTime - CSOnTime) × (TimeParaGranularity + 1) + 0.5 × (OEExtraDelay - CSExtraDelay)) × GPMC_FCLK(14)

(4)

D = PageBurstAccessTime × (TimeParaGranularity + 1) × GPMC_FCLK(14)

(5)

E = ((WEOnTime - CSOnTime) × (TimeParaGranularity + 1) + 0.5 × (WEExtraDelay - CSExtraDelay)) × GPMC_FCLK(14)

(6)

F = ((WEOffTime - CSOnTime) × (TimeParaGranularity + 1) + 0.5 × (WEExtraDelay - CSExtraDelay)) × GPMC_FCLK(14)

(7)

G = Cycle2CycleDelay × GPMC_FCLK(14)

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TDA4VM-Q1, TDA4VM

SPRSP36K – SEPTEMBER 2021 – REVISED APRIL 2024

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