TDA4VM21 datasheet(244/331 Pages) TI

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6.9.5.12.3 GPMC and NAND Flash — Asynchronous Mode

Section 6.9.5.12.3.1 and Section 6.9.5.12.3.2 assume testing over the recommended operating conditions and

electrical characteristic conditions below (see Figure 6-74 through Figure 6-77).

6.9.5.12.3.1 GPMC and NAND Flash Timing Requirements – Asynchronous Mode

NO.

MODE(4)

MIN

MAX

UNIT

133 MHz(5)

GNF12(1)

tacc(d)

Access time, input data GPMC_AD[15:0](3) div_by_1_mode;

J(2)

(1)

The GNF12 parameter illustrates the amount of time required to internally sample input data. It is expressed in number of GPMC

functional clock cycles. From start of the read cycle and after GNF12 functional clock cycles, input data is internally sampled by the

active functional clock edge. The GNF12 value must be stored inside AccessTime register bit field.

(2)

J = AccessTime × (TimeParaGranularity + 1) × GPMC_FCLK(3)

(3)

GPMC_FCLK is general-purpose memory controller internal functional clock period in ns.

(4)

For div_by_1_mode:

•

GPMC_CONFIG1_i Register: GPMCFCLKDIVIDER = 0h:

–

GPMC_CLK frequency = GPMC_FCLK frequency

(5)

For 133 MHz:

•

CTRLMMR_GPMC_CLKSEL[1-0] CLK_SEL = 00 = MAIN_PLL0_HSDIV3_CLKOUT

6.9.5.12.3.2 GPMC and NAND Flash Switching Characteristics – Asynchronous Mode

NO.

PARAMETER

MODE

(15)

MIN

MAX

UNIT

133 MHz

(16)

GNF0 tw(wenV)

Pulse duration, output write enable GPMC_WEn

valid

div_by_1_mode;

A(1)

GNF1 td(csnV-wenV)

Delay time, output chip select GPMC_CSn[i](13)

valid to output write enable GPMC_WEn valid

div_by_1_mode;

B(2)-2.55 B(2)+2.65

GNF2 tw(cleH-wenV)

Delay time, output lower-byte enable and

command latch enable GPMC_BE0n_CLE high to

output write enable GPMC_WEn valid

div_by_1_mode;

C(3)-2.55 C(3)+2.65

GNF3 tw(wenV-dV)

Delay time, output data GPMC_AD[15:0] valid to

output write enable GPMC_WEn valid

div_by_1_mode;

D(4)-2.55 D(4)+2.65

GNF4 tw(wenIV-dIV)

Delay time, output write enable GPMC_WEn

invalid to output data GPMC_AD[15:0] invalid

div_by_1_mode;

E(5)-2.55 E(5)+2.65

GNF5 tw(wenIV-cleIV)

Delay time, output write enable GPMC_WEn

invalid to output lower-byte enable and command

latch enable GPMC_BE0n_CLE invalid

div_by_1_mode;

F(6)-2.55 F(6)+2.65

GNF6 tw(wenIV-CSn[i]V) Delay time, output write enable GPMC_WEn

invalid to output chip select GPMC_CSn[i](13)

invalid

div_by_1_mode;

G(7)-2.55 G(7)+2.65

GNF7 tw(aleH-wenV)

Delay time, output address valid and address latch

enable GPMC_ADVn_ALE high to output write

enable GPMC_WEn valid

div_by_1_mode;

C(3)-2.55 C(3)+2.65

GNF8 tw(wenIV-aleIV)

Delay time, output write enable GPMC_WEn

invalid to output address valid and address latch

enable GPMC_ADVn_ALE invalid

div_by_1_mode;

F(6)-2.55 F(6)+2.65

GNF9 tc(wen)

Cycle time, write

div_by_1_mode;

H(8)

GNF10 td(csnV-oenV)

Delay time, output chip select GPMC_CSn[i](13)

valid to output enable GPMC_OEn_REn valid

div_by_1_mode;

I(9)-2.55

I(9)+2.65

GNF13 tw(oenV)

Pulse duration, output enable GPMC_OEn_REn

valid

div_by_1_mode;

K(10)

GNF14 tc(oen)

Cycle time, read

div_by_1_mode;

L(11)

GNF15 tw(oenIV-CSn[i]V)

Delay time, output enable GPMC_OEn_REn

invalid to output chip select GPMC_CSn[i](13)

invalid

div_by_1_mode;

M(12)-2.55

(12)+2.65

(1)

A = (WEOffTime - WEOnTime) × (TimeParaGranularity + 1) × GPMC_FCLK(14)

TDA4VM-Q1, TDA4VM

SPRSP36K – SEPTEMBER 2021 – REVISED APRIL 2024

www.ti.com

244

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