MCP16502 datasheet(21/86 Pages) MICROCHIP

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DS20006275D-page 21

MCP16502

4.3.4

PWRHLD, LPM, HPM AND POWER

STATES DEFINITIONS

PWRHLD, LPM and HPM define different power states

which are illustrated in Table 4-2. These are default

definitions for the targeted typical application scenario

of the SAMA5D2 MPU when powering LPDDR2 DDR

memories (MCP16502AC), and therefore, may be

different for other application configurations and product

variants.

The logic value of the HPM input pin is masked

(processed by the internal logic as ‘0’) until a specific

I2C command is issued (HPMEN bit must be set to ‘1’),

because HPM is a generic GPIO with a status at the

MPU power-up time that can be undefined.

After the software has issued the unmask HPM

command through I2C, it is safe to assume that the

HPM status is well defined and the HPM signal can be

used to enter and exit the High-Performance mode.

Other logic combinations of PWRHLD, LPM and HPM

(occurring after the HPM unmasking) are forbidden.

The initial state is the OFF state (shutdown).

The process by which the MCP16502 abandons the

OFF state and enters the other possible power states is

defined as the power-up sequence, which is described

in Section 4.4.1 “Typical Power-up Sequence and

Timing”. The following state diagram in Figure 4-2 illus-

trates the power states of MCP16502 and their typical

and/or permissible dynamic transitions.

TABLE 4-2:

DEFAULT POWER STATES DEFINITION (MCP16502AC)

PWRHLD LPM HPM

Buck1

Buck2

Buck3

Buck4

LDO1 LDO2 nRSTO

Power State

OFF

Low

OFF

Auto-PFM

OFF

Auto-PFM

OFF

Low

Hibernate mode

Auto-PFM

OFF

High-Z Low-Power mode

FPWM

OFF

High-Z Active

FPWM

OFF

High-Z High-Performance

Active (only for

SAMA7G5, not used

by SAMA5D2,

SAM9X6, SAM9X7)

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