MCP16502 datasheet(73/86 Pages) MICROCHIP

73 / 86 page

 2019-2022 Microchip Technology Inc. and its subsidiaries

DS20006275D-page 73

MCP16502

5.2

Dynamic Voltage Scaling (DVS)

Operation (for SAMA7G5 Only)

Dynamic Voltage Scaling (DVS) is used by the

SAMA7G5 MPU to momentarily increase both the

VDDCPU voltage and clock frequency in order to

execute heavy computational tasks much faster.

DVS can be implemented in two different ways:

• Write in the relevant HPM registers (typically

OUT4-HPM, 0x43) the new voltage code, and

then (after unmasking the HPM pin) execute the

voltage change by raising the HPM pin; or

• Write the new voltage code in the relevant register

for the current power state.

Indeed, from the MCP16502 perspective, Dynamic

Voltage Scaling is not a special mode of operation.

When the state machine moves from one state to

another, and the content of the regulator voltage in the

new state is different from the previous one (assuming

the regulator is turned on in both the initial and final

state), the output voltage of the regulator will be auto-

matically updated in 25 mV (or 50 mV for Buck1 and

LDOs) increments/decrements to reach the value

which is defined for the final state.

This also happens if the regulator voltage is updated

through I2C without any power mode state change. The

step rate is programmable and it is derived from the

switching frequency clock. The values are described in

Section 4.5.6 “Dynamic Voltage Scaling Rate

Programming Bits (tramp)”.

FIGURE 5-1:

Diagram and Parameters.

Internal filtering time constants for the reference DAC

steps and the finite response time of the control loop

help in smoothing out the resulting ramp shape visible

at the output of the regulator(s).

During DVS transitions:

• The Buck converters will operate in FPWM to

allow a predictable transition time in both the

rising and falling DVS transitions.

• LDO: When the transition happens in the negative

direction (i.e., decreasing voltage), the active

discharge load will be activated during the

transition in order to speed up the transition time.

This is to facilitate the support of dual voltage

SD cards.

The POK will not be deasserted during rising DVS

transitions because of change in the reference (DAC)

voltage. During DVS transition, changes in POK logic

value are inhibited until the transition has completed.

5.3

HPM Pin/HPMPEN Bit

The HPM pin is meant to be driven by a GPIO of the host

for the purpose of entering a Software-Defined

High-Performance mode. Its usage is optional and it

should be connected to ground if it is not used.

SAMA7G5 MPUs could use the HPM pin to switch

Buck4 (VDDCPU rail) to higher voltage, such that

higher clock frequencies can be supported (DVS oper-

ation, see Section 5.2 “Dynamic Voltage Scaling

(DVS) Operation (for SAMA7G5 Only)”). The

required overdrive voltage level in HPM mode needs to

be defined by I2C prior to entering DVS operation. If no

action is taken, the HPM voltage value will default to the

Active mode default value.

The HPM pin needs to be enabled (unmasked) through

I2C by setting the HPMPEN bit in the SYS-CFG

will be insensitive to the HPM pin level, which will

always appear internally as a logic ‘0’.

The HPMPEN bit is not automatically cleared due to a

start-up or to a restart sequence after a Fault. Also, the

DVS voltage level definition stored in the HPM registers

is not reset to the Active mode level. Therefore, if for

any reason the HPM pin remains high (or returns to

high logic level) during the start-up/restart sequence

while the HPMPEN bit has been previously set, the

MCP16502 will move to the High-Performance mode

immediately after the start-up/restart sequence has

successfully terminated. Thus, if the DVS voltage level

defined in HPM mode is different than the voltage level

defined in Active mode, the channel under consider-

ation will immediately move to the HPM mode voltage

level as soon as nRSTO is deasserted.

If the behavior described above is not desirable, the

following countermeasures can be considered:

• Connect the HPM pin to a GPIO which is low by

default at start-up.

• Clear by software the relevant GPIO at the

beginning of the software execution/configuration

routine and/or clear the HPMPEN bit by an I2C

command.

Also note that the channel (typically Buck1, VDDIO)

powering the host voltage domain, to which the GPIO

driving the HPM pin belongs, should always be defined

as ON state in HPM mode.

VOUT_FIN

25 mV

TRANS

VOUT

time

VOUT_INIT

tramp

AVERAGE

RAMP RATE

MCP16502 Datasheet(PDF) 73 Page - Microchip Technology

MCP16502 Datasheet(HTML) 73 Page - Microchip Technology

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86

Datasheet Download

Link URL