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MCP16502 Datasheet(PDF) 71 Page - Microchip Technology |
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MCP16502 Datasheet(HTML) 71 Page - Microchip Technology |
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71 / 86 page ![]() 2019-2022 Microchip Technology Inc. and its subsidiaries DS20006275D-page 71 MCP16502 4.8.3.4 Block Read (Auto-Increment Mode) This command reads a block of bytes, starting from a designated register that is specified through the com- mand byte. The address gets incremented by one automatically and the registers are read in order starting from the address provided by the command byte. The Block/Auto-Increment Read command is as follows, whereas the timing diagram is illustrated in Figure 4-15. 1. Send Start sequence. 2. Send 7-bit target address. 3. Send the R/W bit = 0 to indicate a Write operation. 4. Wait for Acknowledge from the target. 5. Send the command byte – initial address that needs to be read. 6. Wait for Acknowledge from the target. 7. Send Start sequence again (Repeated Start, Sr). 8. Send the 7-bit target address. 9. Send R/W bit = 1 to indicate a Read operation. 10. Wait for Acknowledge from the target. 11. Receive the 8-bit data from the Target register indicated in Step 5, starting from the MSB. 12. Acknowledge from the host receiver. 13. Receive the 8-bit data from the next register, starting from the MSB. 14. Acknowledge from the host receiver. 15. Repeat Steps 13 and 14 until the last byte. 16. Stop sequence is sent. In Block Read, the register order will be automatically incremented by one step, regardless of the register order. So, for example, after reading from register loca- tion 0x15, the next register address to be read will be 0x16, not 0x20. Reading from non-existent or not accessible register addresses will stream out 0xFF. Also note that if the host keeps reading data beyond the last register location, the MCP16502 streams out 0xFF (all ‘1‘s). There is no register address wrap-around. In Block Read Auto-Increment mode, the host receiver must signal an end-of-data to the transmitter by not generating an Acknowledge on the last byte that has been clocked out of the target. In this event, the trans- mitter must leave the data line as high to enable the host to generate a Stop condition. FIGURE 4-15: I2C Block Read. 4.8.3.5 I2C Interface Disable While not necessarily contained in a well-designed implementation, the MCP16502 also supports I2C interface disabling. This is achieved by issuing three separated single Write commands as follows (ADDRESS equals the device address in 7-bit format, default = 0x5B): 1. ADDRESS = 0x5B, COMMAND = 0xEA, DATA = 0xBD 2. ADDRESS = 0x5B, COMMAND = 0xE9, DATA = 0xBD 3. ADDRESS = 0x5B, COMMAND = 0xEC, DATA = 0xBD Upon an ACK of the last byte, the I2C interface will no longer respond to the device address or any other bus transaction. To enable the I2C interface again, power (SVIN) must be cycled. Note: On the last byte, the host receiver issues a NACK in place of an ACK to signal the end of the data transfer. SDA S 0 A A Start Condition ACK from Address Command Byte ACK from Sr 1 A A (Repeated) Start Condition R/W ACK from Address Data from Register X+n Stop Condition DATA (first byte) R/W R/W At this moment, -Transmitter becomes -Receiver and Receiver becomes Transmitter P (cont.) ** * (cont.) ** * (cont.) ** * A Data from Register X DATA (first byte) Data from Register X+1 DATA (first byte) A |
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