MCP16502 datasheet(29/86 Pages) MICROCHIP

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DS20006275D-page 29

MCP16502

FIGURE 4-9:

Entering Hibernate Mode

Timing Diagram.

From the Hibernate state, the system can:

Move to OFF state (if LPM also goes low, the

VOUT2 can be immediately turned off); or

Initiate another start-up sequence (with the

exception of Buck2 which is already active and

has its SEQEN = 1) by a low-to-high transition of

PWRHLD.

The timing diagram of a start-up sequence from Hibernate

mode is shown in Figure 4-10. After the assertion of

PWRHLD, the MPU may deassert LPM at any time. Due

to internal filtering, simultaneous transition of LPM and

PWRHLD is allowed (hold time t5 can be 0 µs).

Depending on the time at which LPM is deasserted, the

MCP16502 may transition through the Low-Power

state or not.

FIGURE 4-10:

Start-Up Sequence Exiting

Hibernate Mode Timing Diagram.

Similar to Buck2, any other regulator defined as ON

state in the Hibernate state with its bit SEQEN = 1, will

not be turned off when exiting the Hibernate state for a

new start-up sequence.

If the regulator is defined as ON state in the Hibernate

state, but its bit SEQEN = 0, it will be turned off as soon

as the new start-up sequence is initiated.

In conclusion, for a regulator to stay turned on

continuously from the Hibernate state throughout the

new start-up sequence, two conditions must be

satisfied:

The regulator is set as ON in the Hibernate

state.

SEQEN bit = 1.

VIN

VDDIO

(VOUT1)

PWRHLD

VDDIODDR

(VOUT2)

VDDCORE

(VOUT3)

nRSTO

time

LPM

VDDCPU

(VOUT4)

Where:

t5 = Setup time, LPM = 1 to PWRHLD = 0:

Min. 0 µs (internal filtering applies)

t6 = Delay from PWRHLD deasserted to

nRSTO asserted: Min. 0 µs,

max. 10 µs (not a strict requirement)

t7 = Delay from nRSTO asserted to first

VOUTX turn-off: Min. 0 µs, max. 10 µs

(not a strict requirement)

Note:

Upon exit of Hibernate mode, Buck2 is not

part of the sequence because it is already

turned on (being in Auto-PFM mode) and

its SEQEN = 1. However, also depending

on the instant at which the MPU deasserts

LPM, it can toggle to FPWM mode at the

time nRSTO is deasserted.

VIN

VDDIO

(VOUT1)

PWRHLD

VDDIODDR

(VOUT2)

VDDCORE

(VOUT3)

nRSTO

time

LPM

Hibernate

Low Power

Active

Power

State

VDDCPU

(VOUT4)

Where:

t1 = Delay from PWRHLD asserted to first

supply VOUT1 starting (SEQ[1:0] = 00,

default DELAY[2:0] = 001; i.e., 0.5 ms)

t3 = Time from VOUT1 established to VOUT3,

VOUT4 starting (SEQ[1:0] = 10, default

DELAY[2:0] = 100; i.e., 4 ms)

t4 =Time from VOUT3, VOUT4 established to

nRSTO deassertion (default

RSTDLY[2:0] = 100; i.e., 16 ms)

t5 = Minimum hold time, PWRHLD = 1 to

LPM = 0: Min. 0 µs (internal filtering

applies)

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