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R2023K Datasheet(PDF) 12 Page - RICOH electronics devices division

Part # R2023K
Description  2-wire Serial Interface Real Time Clock IC
PDF  50 Pages
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Manufacturer  RICOH [RICOH electronics devices division]
Direct Link  http://www.ricoh.com
Logo RICOH - RICOH electronics devices division

R2023K Datasheet(HTML) 12 Page - RICOH electronics devices division

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R2023K/T
12
Register Settings
• Control Register 1 (ADDRESS Eh)
D7
D6
D5
D4
D3
D2
D1
D0
WALE
DALE
12 /24
CLEN2
TEST
CT2
CT1
CT0
(For Writing)
WALE
DALE
12 /24
CLEN2
TEST
CT2
CT1
CT0
(For Reading)
0
0
0
0
0
0
0
0
Default Settings *)
*)
Default settings:
Default value means read / written values when the PON bit is set to “1” due to VDD
power-on from 0 volts.
(1) WALE, DALEAlarm_W Enable Bit, Alarm_D Enable Bit
WALE,DALE
Description
0
Disabling the alarm interrupt circuit (under the control of the settings
of the Alarm_W registers and the Alarm_D registers).
(Default)
1
Enabling the alarm interrupt circuit (under the control of the settings
of the Alarm_W registers and the Alarm_D registers)
(2) 12 /24
12
/24-hour Mode Selection Bit
12 /24
Description
0
Selecting the 12-hour mode with a.m. and p.m. indications.
(Default)
1
Selecting the 24-hour mode
Setting the 12 /24 bit to 0 and 1 specifies the 12-hour mode and the 24-hour mode, respectively.
24-hour mode
12-hour mode
24-hour mode
12-hour mode
00
12 (AM12)
12
32 (PM12)
01
01 (AM 1)
13
21 (PM 1)
02
02 (AM 2)
14
22 (PM 2)
03
03 (AM 3)
15
23 (PM 3)
04
04 (AM 4)
16
24 (PM 4)
05
05 (AM 5)
17
25 (PM 5)
06
06 (AM 6)
18
26 (PM 6)
07
07 (AM 7)
19
27 (PM 7)
08
08 (AM 8)
20
28 (PM 8)
09
09 (AM 9)
21
29 (PM 9)
10
10 (AM10)
22
30 (PM10)
11
11 (AM11)
23
31 (PM11)
Setting the 12 /24 bit should precede writing time data
(3) CLEN2
32kHz Clock Output Bit 2
CLEN2
Description
0
Enabling the 32-kHz clock circuit
(Default)
1
Disabling the 32-kHz clock circuit
Setting the CLEN2 bit or the CLEN1 bit (D3 in the control register 2) to 0, and the CLKC pin to high
specifies generating clock pulses with the oscillation frequency of the 32.768-kHz crystal oscillator for output
from the 32KOUT pin. Conversely, setting both the CLEN1 and CLEN2 bit to 1 or CLKC pin to low
specifies disabling (”L”) such output.
(4) TEST
Test Bit
TEST
Description
0
Normal operation mode.
(Default)
1
Test mode.
The TEST bit is used only for testing in the factory and should normally be set to 0.



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