R2023K datasheet(40/50 Pages) RICOH

40 / 50 page

R2023K/T

this circuit when set to 1 and to disable it when set to 0.

When intended for reading, the flag bits can be used to

monitor alarm interrupt signals.

When intended for writing, the flag bits will cause no event when set to 1 and will

drive high (disable) the alarm interrupt circuit when set to 0.

The enable bits will not be affected even when the flag bits are set to 0.

In this event, therefore, the alarm

interrupt circuit will continue to function until it is driven low (enabled) upon the next occurrence of a match between

current time and preset alarm time.

The alarm function can be set by presetting desired alarm time in the alarm registers (the Alarm_W Registers for

the day-of-week digit settings and both the Alarm_W Registers and the Alarm_D Registers for the hour and minute

digit settings) with the WALE and DALE bits once set to 0 and then to 1 in the Control Register 1.

Note that the

WALE and DALE bits should be once set to 0 in order to disable the alarm interrupt circuit upon the coincidental

occurrence of a match between current time and preset alarm time in the process of setting the alarm function.

current time =

preset alarm time

WALE

←1

(DALE)

Interval (1min.) during which a match

between current time and preset alarm time

occurs

current time =

preset alarm time

WAFG

←0

(DAFG)

INTRB

(INTRA)

WALE

←1

(DALE)

WALE

←1

(DALE)

current time =

preset alarm time

WALE

←0

(DALE)

current time =

preset alarm time

INTRB

(INTRA)

After setting WALE(DALW) to 0, Alarm registers is set to current time, and WALE(DALE) is set to 1,

INTRB ( INTRA ) will be not driven to “L” immediately, INTRB ( INTRA ) will be driven to “L” at next alarm setting

time.

• Periodic Interrupt

Setting of the periodic selection bits (CT2 to CT0) enables periodic interrupt to the CPU. There are two waveform

modes: pulse mode and level mode.

In the pulse mode, the output has a waveform duty cycle of around 50%. In

the level mode, the output is cyclically driven low and, when the CTFG bit is set to 0, the output is return to High

(OFF).

Description

CT2

CT1

CT0

Wave form

mode

Interrupt Cycle and Falling Timing

OFF(H)

(Default)

Fixed at “L”

Pulse Mode *1)

2Hz(Duty50%)

Pulse Mode *1)

1Hz(Duty50%)

Level Mode *2)

Once per 1 second (Synchronized with

Second counter increment)

Level Mode *2)

Once per 1 minute (at 00 seconds of every

Minute)

Level Mode *2)

Once per hour (at 00 minutes and 00

Seconds of every hour)

Level Mode *2)

Once per month (at 00 hours, 00 minutes,

and 00 seconds of first day of every month)

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