R2023K datasheet(15/50 Pages) RICOH

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R2023K/T

(5) CLEN1

32kHz Clock Output Bit 1

CLEN1

Description

Enabling the 32-kHz clock circuit

(Default)

Disabling the 32-kHz clock circuit

Setting the CLEN1 bit or the CLEN2 bit (D4 in the control register 1) to 0, and the CLKC pin to high

specifies generating clock pulses with the oscillation frequency of the 32.768-kHz crystal oscillator for output

from the 32KOUT pin. Conversely, setting both the CLEN1 and CLEN2 bit to 1 or CLKC pin to low

specifies disabling (”L”) such output.

(6) CTFG

Periodic Interrupt Flag Bit

CTFG

Description

Periodic interrupt output = “H”

(Default)

Periodic interrupt output = “L”

The CTFG bit is set to 1 when the periodic interrupt signals are output from the INTRA pin (“L”).

The

CTFG bit accepts only the writing of 0 in the level mode, which disables (“H”) the INTRA pin until it is

enabled (“L”) again in the next interrupt cycle. Conversely, setting the CTFG bit to 1 causes no event.

(7) WAFG,DAFG

Alarm_W Flag Bit and Alarm_D Flag Bit

WAFG,DAFG

Description

Indicating a mismatch between current time and preset alarm time

(Default)

Indicating a match between current time and preset alarm time

The WAFG and DAFG bits are valid only when the WALE and DALE have the setting of 1, which is caused

approximately 61

µs after any match between current time and preset alarm time specified by the Alarm_W

registers and the Alarm_D registers.

The WAFG (DAFG) bit accepts only the writing of 0.

INTRA ( INTRB ) pin outputs off (“H”) when this bit is set to 0.

And INTRA ( INTRB )

pin outputs “L”

again at the next preset alarm time.

Conversely, setting the WAFG and DAFG bits to 1 causes no event.

The WAFG and DAFG bits will have the reading of 0 when the alarm interrupt circuit is disabled with the

WALE and DALE bits set to 0.

The settings of the WAFG and DAFG bits are synchronized with the output of

the INTRA ( INTRB ) pin as shown in the timing chart below.

INTRB (INTRA) Pin

Writing of 0 to

WAFG(DAFG) bit

WAFG(DAFG) Bit

(Match between

current time and

preset alarm time)

Approx. 61

µs

Approx. 61

µs

Writing of 0 to

WAFG(DAFG) bit

(Match between

current time and

preset alarm time)

(Match between

current time and

preset alarm time)

R2023K Datasheet(PDF) 15 Page - RICOH electronics devices division

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