AM67 datasheet(104/237 Pages) TI

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6.9.3 System Timing

For more details about features and additional description information on the subsystem multiplexing signals,

see the corresponding subsections within Signal Descriptions and Detailed Description sections.

6.9.3.1 Reset Timing

Tables and figures provided in this section define timing conditions, timing requirements, and switching

characteristics for reset related signals.

Table 6-6. Reset Timing Conditions

PARAMETER

MIN

MAX

UNIT

INPUT CONDITIONS

SRI

Input slew rate

VDD(1) = 1.8V

0.0018

V/ns

VDD(1) = 3.3V

0.0033

V/ns

OUTPUT CONDITIONS

Output load capacitance

30 pF

(1)

VDD stands for corresponding power supply. For more information on the power supply name and the corresponding ball(s), see

POWER column of the Pin Attributes table.

Table 6-7. MCU_PORz Timing Requirements

see Figure 6-7

NO.

PARAMETER

MIN

MAX UNIT

RST1

th(SUPPLIES_VALID - MCU_PORz)

Hold time, MCU_PORz active (low) at Power-up

after supplies valid (using external crystal circuit)

9500000

RST2

Hold time, MCU_PORz active (low) at Power-up

after supplies valid and external clock stable (using

external LVCMOS clock source)

1200

RST3

tw(MCU_PORzL)

Pulse Width, MCU_PORz low after Power-up

(without removal of Power or system reference

clock MCU_OSC0_XI/XO)

1200

Figure 6-7. MCU_PORz Timing Requirements

AM67, AM67A

SPRSPA3A – MARCH 2024 – REVISED SEPTEMBER 2024

www.ti.com

104

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