440GR datasheet(65/82 Pages) AMCC

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AMCC Proprietary

440GR – PPC440GR Embedded Processor

Preliminary Data Sheet

Revision 1.16 – July 19, 2006

I/O Specifications

Table 16. Peripheral Interface Clock Timings

Parameter

Min

Max

Units

Notes

PCIClk input frequency (asynchronous mode)

–

66.66

MHz

PCIClk period (asynchronous mode)

–

PCIClk input high time

40% of nominal period

60% of nominal period

PCIClk input low time

40% of nominal period

60% of nominal period

EMCMDClk output frequency

–

2.5

MHz

EMCMDClk period

400

–

EMCMDClk output high time

160

–

EMCMDClk output low time

160

–

EMCTxClk input frequency MII(RMII)

2.5(5)

25(50)

MHz

EMCTxClk period MII(RMII)

40(20)

400(200)

EMCTxClk input high time

35% of nominal period

–

EMCTxClk input low time

35% of nominal period

–

EMCRxClk input frequency MII(RMII)

2.5(5)

25(50)

MHz

EMCRxClk period MII(RMII)

40(20)

400(200)

EMCRxClk input high time

35% of nominal period

–

EMCRxClk input low time

35% of nominal period

–

PerClk (and OPB Clock) output frequency (for ext. master or

sync. slaves)

–66.66

MHz

PerClk period

–

PerClk output high time

50% of nominal period

66% of nominal period

PerClk output low time

33% of nominal period

50% of nominal period

UARTSerClk input frequency

–

1000/(2TOPB

1+2ns)

MHz

UARTSerClk period

2TOPB+2

–ns

UARTSerClk input high time

TOPB+1

–ns

UARTSerClk input low time

TOPB+1

–ns

TmrClk1 input frequency

–

100

MHz

TmrClk1 period

–

TmrClk1 input high time

40% of nominal period

60% of nominal period

TmrClk1 input low time

40% of nominal period

60% of nominal period

Notes:

1. TOPB is the period in ns of the OPB clock. The internal OPB clock runs at 1/2 the frequency of the PLB clock. The maximum OPB clock

frequency is 66.66 MHz.

2. See Table 7 for information on the TmrClk2 signal.

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