440GR datasheet(76/82 Pages) AMCC

76 / 82 page

AMCC Proprietary

Revision 1.16 – July 19, 2006

Preliminary Data Sheet

440GR – PPC440GR Embedded Processor

Example 1:

If the data-to-PLB clock timing is as shown in the example below, then the read clock is not delayed and the Stage

1 data is sampled at (1). Except for small, low frequency memory systems with the memory located physically close

to the PPC440GR, it is unlikely that Stage 1 data can be sampled. When the data comes later, it is necessary to

sample Stage 2 or Stage 3 data. (see Examples 2 and 3). Another way to get the desired data-to-PLB timing to

allow Stage 1 sampling is to buffer MemClkOut0 and skew it enough to guarantee the timing. In this example, TT is

controlled and set by the software.

Figure 11. DDR SDRAM Read Cycle Timing—Example 1

DQS at pin

PLB Clock

TSIN

TDIN = Delay from data at package pin to D on Stage 1 FF.

TSIN = Delay from DQS at package pin to C on Stage 1 FF.

Data at pin

DQS Stage 1 C

TDIN

Data in Stage 1 D

Data out Stage 1

High

Low

Data in at RDSP

High

Low

with no ECC

TP = Propagation delay through FFs

TT = Propagation delay, Stage 1 input to RDSP input w/o ECC

Data out RDSP

High

Low

(1)

440GR Datasheet(PDF) 76 Page - Applied Micro Circuits Corporation