440GR datasheet(79/82 Pages) AMCC

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AMCC Proprietary

440GR – PPC440GR Embedded Processor

Preliminary Data Sheet

Revision 1.16 – July 19, 2006

Initialization

The PPC440GR provides the option for setting initial parameters based on default values or by reading them from

a slave PROM attached to the IIC0 bus (see “Serial EEPROM” below). Some of the default values can be altered

by strapping on external pins (see “Strapping” below).

Strapping

While the SysReset input pin is low (system reset), the state of certain I/O pins is read to enable certain default

initial conditions prior to PPC440GR start-up. The actual capture instant is the nearest reference clock edge before

the deassertion of reset. These pins must be strapped using external pull-up (logical 1) or pull-down (logical 0)

resistors to select the desired default conditions. These pins are used for strap functions only during reset.

Following reset they are used for normal functions. The signal names assigned to the pins for normal operation are

shown in parentheses following the pin number.

The following table lists the strapping pins along with their functions and strapping options:

Serial EEPROM

During reset, initial conditions other than those obtained from the strapping pins can be read from a ROM device

connected to the IIC0 port. At the de-assertion of reset, if the bootstrap controller is enabled, the PPC440GR

sequentially reads 16B from the ROM device on the IIC0 port and sets the SDR0_SDSTP0, SDR0_SDSTP1,

SDR0_SDSTP2 and SDR0_SDSTP3 registers accordingly.

The initialization settings and their default values are covered in detail in the PowerPC 440GR User’s Manual.

Table 24. Strapping Pin Assignments

Function

Option

Ball Strapping

R25

(UART0_DCD)

U26

(UART0_DSR)

V26

(UART0_CTS)

Serial device is disabled. Each of the six options (A–

F) is a combination of boot source, boot-source

width, and clock frequency specifications. Refer to

the IIC Bootstrap Controller chapter in the

PPC440GR Embedded Processor User’s Manual for

details.

000

001

010

011

100

110

Serial device is enabled. The option being selected is

the IIC0 slave address that will respond with

strapping data.

Note: If reading of configuration data from the serial

device fails, the PPC440GR defaults to configuration

G (0xA8)

101

H (0xA4)

111

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