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AS8267 Datasheet(PDF) 69 Page - ams AG

Part # AS8267
Description  Single-Phase 2-Current Energy Measurement Integrated Circuits with Microcontroller, RTC, Programmable Multi-Purpose I/Os
PDF  136 Pages
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Manufacturer  AMSCO [ams AG]
Direct Link  http://www.ams.com
Logo AMSCO - ams AG

AS8267 Datasheet(HTML) 69 Page - ams AG

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Data Sheet AS8267 / AS8268
Revision 1.0, 19-Jun-07
Page 69 of 136
Clock Divider Register (SSPCLKDIV, 9401h)
The clock divider register contains control bits to configure the clock-divider, to set-up the serial-clock SC, to
enable the SPI and to select master or slave mode.
MSB
LSB
ENBL
CIDLE
CPHA
M/S
CLKDIV.3
CLKDIV.2
CLKDIV.1
CLKDIV.0
Bit
Symbol
Function
7
ENBL
SPI enable. Enables the SPI interface
1: enable
0: disable
CIDLE
Bit6
CPHA
Bit5
SC Idle
Data shifted
out on SC
Input sampled
on SC
0
0
0
falling
rising
0
1
0
rising
falling
6
CIDLE
Serial clock SC idle state
1: SC idles high
0: SC idles low
1
0
1
rising
falling
1
1
1
falling
rising
5
CPHA
Serial clock SC phase
Data is samples and shifted out
according to CIDLE/CPHA
Note: The CIDLE/CPHA set at 1 1 is used internally by most
standard available EEPROMs
4
M/S
Master/Slave mode
1: Master mode, must be ‘1’
0: Slave mode
Bit3
Bit2
Bit1
Bit0
SC-Rate
0
0
0
0
1 : 2
0
0
0
1
1 : 4
0
0
1
0
1 : 8
3
CLKDIV.3
0
0
1
1
1 : 16
0
1
0
0
1 : 32
0
1
0
1
1 : 64
0
1
1
0
1 : 128
2
CLKDIV.2
0
1
1
1
1 : 256
1
0
0
0
1 : 512
1
0
0
1
1 : 1,024
1
0
1
0
1 : 2,048
1
CLKDIV.1
1
0
1
1
1 : 4,096
1
1
0
0
1 : 8,192
1
1
0
1
1 : 16,384
1
1
1
0
1 : 32,768
0
CLKDIV.0
Clock divider exponent
In master mode, SPI output clock SC is
MCU_CLK / 2
CLKDIV+1
1
1
1
1
1 : 65,536
The SPI output clock SC, which is derived from the mcu clock (mcu_clk) may be divided down as shown in the
table above.
It is important to note, that the mcu_clk may also be divided down as described under MCUCLKDIV Register
(‘mcu_clk’). Therefore the SPI output clock SC is also dependent on the programming of the mcu_clk
frequency.



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