AS8267 datasheet(70/136 Pages) AMSCO

70 / 136 page

Data Sheet AS8267 / AS8268

Revision 1.0, 19-Jun-07

Page 70 of 136

Recommended programming for 3.579545MHz mcu clock rate, SPI enabled, SC clock phase = ‘11’, master:

Value

SC Clock Rate

1.74MHz

F0h

0.895MHz

F1h

0.447MHz

F2h

Status Register (SSPSTAT, 9402h)

MSB

LSB

ITRA

IOVR

ICOL

CSI

Bit

Symbol Function

ITRA

Transmission complete interrupt issued. Issued after new data word is available in data-register (slave

configuration), or if data-register has been shifted out after write access (master configuration)

IOVR

Overrun interrupt issued. Issued if ITRA is still set from previous transmission and new data arrives

(master and slave configuration)

ICOL

Write-collision interrupt issued. Issued if data-register is written during receive (slave configuration) or

transmit (master configuration)

Not used

CSI

Always ‘0’, has no effect

Not used

Note:

1) Flag-bits change state independent of the state of the corresponding interrupt-enable bit of the control

The SPI interrupt status is captured in the SSPSTAT register. Each interrupt status bit can be masked by the

SSPCON register, which is OR-ed to a single SPI interrupt request signal (SPI_IRQ).

IE.ESPI

(=IE.3)

ITRA

IOVR

ICOL

IETR,

IEOV,

IECO

SPI_IRQ

SSPSTAT

SSPCON

MCU Register

Figure 9:

Block diagram

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