AS8267 datasheet(41/136 Pages) AMSCO

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Data Sheet AS8267 / AS8268

Revision 1.0, 19-Jun-07

Page 41 of 136

For power-saving reasons, the fast oscillator clock is first divided down by a fixed ratio (divide by 5) and then

the programmable divider follows.

div5

programmable divider

Mclk

clk_1hz

div[19:0]

Parameter

Symbol

Min

Typ

Max

Unit

Notes

Input frequency range

fMclk

3.0

3.579545

4.0

MHz

Division factor

1,048,575

The setting of div[19:0] is located in the RTC registers (addresses: 9132h – 9130h)

Note:

1) The division factor n is effective on the frequency Mclk/5. It represents the actual division factor minus 1.

Example: Calculate n for oscillator frequency 3,579,545Hz. The frequency after the div5 is 715,909Hz.

Therefore, n must be 715,909 – 1 = 715,908 to get 1Hz.

2) Setting n = 1 means a division factor of 2.

Real-Time Clock (RTC)

The RTC can be directly accessed from the MCU via a dedicated interface register.

Two alarm registers are provided to indicate a certain time instance, such as the start of a new month. In that

case an interrupt is sent to the MCU. Constant frequency deviations of the crystal that is used can be trimmed

to an accuracy of better than +/-1.4ppm.

A seconds counter is provided which may be used for certain meter calculations. There is only one interrupt

output. The source of the interrupt is indicated in the Control/Status 2 register.

Time/

Calendar

Registers

Alarm

Registers

LP_DIV

Setting

Frequency

Trim

Seconds

Counter

MCU

LP_DIV

RTC

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