AS8267 datasheet(72/136 Pages) AMSCO

72 / 136 page

Data Sheet AS8267 / AS8268

Revision 1.0, 19-Jun-07

Page 72 of 136

8.5.2.

SPI_FLASH Mode

In this mode the SPI operates in slave mode, in which the interface is used to communicate with the internal

Flash memory.

The SPI_Flash block contains an 8-bit instruction register. It is accessed via the MISO pin, with data being

clocked in on the rising edge of SC. The S_N pin must be low. The table below contains the list of the possible

instruction bytes and format for SPI_Flash block operation. All instructions, addresses, and data are

transferred MSB first, LSB last. Data is sampled on the first rising edge of SC after S_N goes low.

Instruction Set

Instruction Name

Instruction

Code

Description

READ

03h

Read data from memory array beginning at selected address

02h

Page Program, moves data to selected memory page

WREN

06h

Set write enable latch (enable write and erase operations)

WRDI

04h

Reset the write enable latch (disable write operations)

RDSR

05h

Read Flash status register (FLASH_STAT, 9700h)

WRSR

01h

Write Flash status register (FLASH_STAT, 9700h)

D8h

Page Erase

C7h

Mass Erase

RESET

E9h

Sets external reset pin (may be used to reset the whole device)

Functional Description

Arbitration

After a write, page erase or mass erase command the Flash memory is busy for some time and no command must be sent.

To handle concurrent access from MCU and the MCU independent interfaces (UART1, SPI via SPI_Flash) to the Flash

memory an arbitration procedure is necessary for the external interfaces:

Send a request to the Flash (Set REQ bit in FLASH_STAT register)

Poll status of Flash until Flash is ready (WIP bit in FLASH_STAT register must be 0)

-> Flash memory is reserved for external interface and MCU remains halted.

Send one or several Flash commands (Flash must not be busy before sending the next Flash command)

Release Flash request (Clear REQ bit in FLASH_STAT register)

-> MCU is running again

Request is needed for all Flash commands

Concurrent access of both MCU independent interfaces is not allowed.

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