AS8267 datasheet(73/136 Pages) AMSCO

73 / 136 page

Data Sheet AS8267 / AS8268

Revision 1.0, 19-Jun-07

Page 73 of 136

Read

The SPI_Flash is selected by pulling S_N low. The 8-bit read instruction is transmitted to the SPI_Flash followed by the 16-bit

address with the MSB (address[15]) of the address word being don’t care. After the correct read instruction and address are

sent, the data stored in the memory at the selected address is shifted out on the MOSI pin. (After an access time of 13

system clocks the Flash data is available in the SPI transit register). The data stored in the memory at the next address can

be read sequentially by continuing to provide clock pulses. The internal address pointer is automatically incremented to the

next higher address after each byte of data is shifted out. When the highest address is reached (7FFFh), the address counter

rolls over to address 0000h allowing the read cycle to be continued indefinitely. Rising the S_N pin terminates the read

operation.

Timing

MISO

MOSI

S_N

High Impedance

Instruction

16 Bit Address

Data Out

Example Read FLASH Sequence

0x01

… … set REQ bit by writing 0x04 to status register

0x04

… -“-

0x05

… read Flash status register until Flash is ready

0x03

… read Flash instruction

0x00

… Start address, e.g. 80h

0x80

… -“-

Dat0

… read byte 0 from address

Dat1

… read byte 1 from address + 1

…

… read bytes as long as you want, after address overrun it restarts at address 0.

10. 0x01

… clear REQ bit by writing 0x00 to status register

11. 0x00

… -“-

Page Program

The whole memory of 32K bytes is split into 512 pages with 64 bytes per page. Each page can be written with 64 bytes at

once or, it can be written byte-wise or in groups of bytes. The addressing order is arbitrary. Prior to any attempt to write data

to the SPI_Flash or status register, the write enable latch must be set by issuing the WREN instruction. Setting S_N low and

then clocking out the proper instruction into the SPI_Flash does this. After all eight bits of the instruction are transmitted; the

S_N must be brought high to set the write enable latch. If the write operation is initiated immediately after the WREN

instruction without S_N being brought high, the data will not be written to the array because the write enable latch will not

have been properly set.

Once the write enable latch is set, the user may proceed by setting the S_N low, issuing a write instruction, followed by the

address, and then the data to be written. Up to 64 bytes of data can be sent to the SPI_Flash before a program cycle is

necessary. The only restriction is that all of the bytes must reside in the same page. An address consists of a page address

(9 bits) and the address in page (6 bits), where the page address = address [15:6] and the address in page is address [5:0]. If

the internal address counter reaches 0x7FFF and the clock continues, the counter will roll over to the first address 0x0000.

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