AS8267 datasheet(47/136 Pages) AMSCO

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Data Sheet AS8267 / AS8268

Revision 1.0, 19-Jun-07

Page 47 of 136

Year Alarm Register (1/2) (9118h/911Dh)

MSB

LSB

yeara.7

yeara.6

yeara.5

yeara.4

yeara.3

yeara.2

yeara.1

yeara.0

These bits represent the year alarm value encoded in BCD format (value from 0 to 99).

Setting the Time

The time can be set by writing to the respective time and calendar registers. When this is done the clock stops,

the WAIT bit is set and the control waits for the WAIT bit to be reset.

When the WAIT bit is reset the clock gate will be opened and the RTC starts running.

Alarms

When time and one of the alarm registers match (seconds = 0), an interrupt is generated. The source of the

interrupt is indicated in the A[1|2]F register bits in the Control/Status 2 register.

The alarm generation can be disabled using the AIE1/2 bits.

When the rest of the chip is off, there is no clock for the MCU interface, hence no alarm will be generated.

The MCU interface is reset with the ‘res’ signal which is coming from the PSM, i.e. all Status 2 bits are reset to

default, which means that after MCU power-up it has to set the appropriate alarms again. (After power-up the

MCU has to check what the time is, and has to decide what the next appropriate alarms will be.)

Seconds Timer (9112h, 9113h)

The seconds counter block, if enabled (SIE bit of Control/Status 2 register), generates an interrupt every n

seconds. ‘n’ is the number of seconds specified in the Seconds Timer registers 9112h (Byte 0) and 9113h (Byte

1). When an interrupt is sent, the flag STF is set.

The Seconds Timer register is not BCD coded.

Seconds counter start value:

0000h

Seconds counter count direction:

Condition for interrupt generation:

Seconds counter register value = Seconds Timer register value

Note: 0000h in the timer register means that no interrupt must be generated.

RTC Calibration (clk_1Hz)

When using the real-time clock (RTC) it is essential that the 1Hz signal to the real-time clock is accurate. There

are many possible external influences on the crystal oscillator frequency including the absolute crystal

frequency itself and the parasitic and oscillator capacitor values.

These influences alone can contribute to a significant change in the oscillator frequency. In this case, it is

necessary to perform a calibration of the 1Hz signal through the ‘Programmable Divider’ located in the 'Low

Power Divider'.

The procedure for trimming the RTC via the 'Programmable Divider' is explained below:

Assuming a crystal frequency of 3.579545 MHz

AS8267 Datasheet(PDF) 47 Page - ams AG

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