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AS8267 Datasheet(PDF) 95 Page - ams AG

Part # AS8267
Description  Single-Phase 2-Current Energy Measurement Integrated Circuits with Microcontroller, RTC, Programmable Multi-Purpose I/Os
PDF  136 Pages
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Manufacturer  AMSCO [ams AG]
Direct Link  http://www.ams.com
Logo AMSCO - ams AG

AS8267 Datasheet(HTML) 95 Page - ams AG

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Data Sheet AS8267 / AS8268
Revision 1.0, 19-Jun-07
Page 95 of 136
Addressing Modes
The MCU comprises all standard 8051 addressing modes. For completeness they are listed here. There are
five types. In two byte instructions the destination is specified first, then the source.
Mode
Examples
Notes
Register addressing
MOV A, R0
Register R0 in I_RAM one out of 4 banks
selected
Direct addressing
MOV R0, A
Moves contents of A to R0
Register indirect addressing
MOV @R0, A
MOVX @DPTR, A
Moves contents of A to location addressed
by R0, or by DPTR
Immediate addressing
MOV R0, #data
Moves immediate #data to R0
Index addressing
MOVC A, @A+DPTR
MOVC A, @A+PC
Moves contents of location addressed by
A+DPTR, or A+PC to A. For reading lookup
tables, applies to program memory only
Interrupt Controller
The 8051 core provides 7 interrupt sources: 2 of them are the same as in the standard 8051, the others are
tied to specific internal sources. Each interrupt causes the program to jump to the corresponding interrupt
vector if the interrupt is enabled in the interrupt enable register (IE). The interrupt priority can be controlled via
the interrupt priority register (IP) in order to override the predefined priority, starting with IP.0 as highest. For
further information on the interrupt sources refer to the appropriate chapters.
Interrupt Enable Register (IE)
Each of the interrupt sources can be individually enabled or disabled by setting the corresponding bit in the IE
register. This register contains a global enable bit EA. By clearing this bit all interrupts can be disabled at
once.
IE
MSB
LSB
EA
ERTC
ES2
ES
ESPI
EIOX
ET0
EDSP
Enable bit = 0 disables the interrupt
Enable bit = 1 enables the interrupt
Interrupt Priority Register (IP)
IP
MSB
LSB
-
PRTC
PS2
PS
PSPI
PIOX
PT0
PDSP
Priority bit = 1 assigns high priority
Priority bit = 0 assigns low priority



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