AS8267 datasheet(96/136 Pages) AMSCO

96 / 136 page

Data Sheet AS8267 / AS8268

Revision 1.0, 19-Jun-07

Page 96 of 136

Interrupt

Source

RTC

UART2

UART1

SPI

MPIO

Timer 0

DSP

Interrupt

Vector

0033h

002Bh

0023h

001Bh

0013h

000Bh

0003h

Note:

Timer0 must have the highest priority in the IP register. No other interrupt should be assigned with a high priority.

Symbol

Position

Function

Priority

IE.7

Disables all interrupt when 0. If EA = 1 each interrupt is

individually enabled due to its enable bit.

ERTC

IE.6

RTC real time clock, interrupt enable bit

Lowest

ES2

IE.5

UART2, serial port, interrupt enable bit

IE.4

UART1, serial port, interrupt enable bit

ESPI

IE.3

SPI serial port, interrupt enable bit

EIOX

IE.2

MPIO external pin, interrupt enable bit

ET0

IE.1

Timer 0, interrupt enable bit

EDSP

IE.0

DSP data available

Highest

Note:

1) Standard 8051 bits

Interrupt Priorities

Each interrupt source can be individually assigned one of two priority levels. A low priority interrupt can always

be interrupted by a higher-priority interrupt, but not by another low priority interrupt. A high-priority interrupt

cannot be interrupted by any other interrupt source.

If the corresponding IP bit is set then this interrupt is serviced first if another interrupt request occurs at the

same time where the IP bit is zero.

Interrupt on the same priority level are serviced due to the internal polling sequence starting with DSP highest

down to RTC lowest.

Symbol

Position

Function

Source Flags

IP.7

PRTC

IP.6

Real time clock, priority bit

TSA, STF, A1F, A2F

PS2

IP.5

UART2 serial port, priority bit

RI, TI

IP.4

UART1 serial port, priority bit

RI, TI

PSPI

IP.3

SPI serial port, priority bit

ITRA

PIOX

IP.2

MPIO external pin, priority bit

in Status 0 / Status 1

PT0

IP.1

Timer 0, priority bit

TF0

PDSP

IP.0

DSP priority bit

dai, alarm

Note:

1) Standard 8051 bits

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