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SN74AC596 Datasheet(PDF) 6 Page - Texas Instruments

Part # SN74AC596
Description  SN74AC596-Q1 Automotive 8-Bit Shift Register With Open-Drain Output Registers
PDF  35 Pages
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Manufacturer  TI [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI - Texas Instruments

SN74AC596 Datasheet(HTML) 6 Page - Texas Instruments

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over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
-40°C to 125°C
UNIT
MIN
TYP
MAX
VOL
IOL = 50µA
1.5V
0.001
0.1
V
1.8V
0.001
0.1
2.5V
0.001
0.1
3V
0.001
0.1
4.5V
0.001
0.1
5.5V
0.001
0.1
IOL = 1mA
1.8V
0.36
IOL = 2mA
2.5V
0.5
IOL = 4mA
3V
0.5
IOL = 12mA
3V
0.5
IOL = 24mA
4.5V
0.5
IOL = 24mA
5.5V
0.5
IOL = 75mA(3)
5.5V
1.65
II
VI = 5.5V or GND
0V to 5.5V
±1
µA
IOZ
VO = VCC or GND
5.5V
±1
µA
ICC
VI = VCC or GND, IO = 0
5.5V
2
µA
CI
VI = VCC or GND
5V
2
pF
CO
VO = VCC or GND
5V
4
pF
CPD (1) (2)
CL = 50pF, F = 1MHz
5V
57
pF
(1)
CPD is used to determine the dynamic power consumption, per channel
(2)
PD= VCC 2xFIx(CPD+ CL) where FI= input frequency, CL= output load capacitance, VCC= supply voltage
(3)
Not more than one output should be tested at a time, and the duration of the test should not exceed 2 ms.
(4)
Applies to QH' output only.
5.6 Timing Characteristics
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
DESCRIPTION
CONDITION
VCC
-40°C to 125°C
UNIT
MIN
MAX
fclock
Clock frequency
1.5V
22
MHz
tw
Pulse duration
RCLK or SRCLK high or low
1.5V
9.2
ns
tw
Pulse duration
SRCLR low
1.5V
5.4
ns
tsu
Setup time
SER before SRCLK↑
1.5V
5.4
ns
tsu
Setup time
SRCLK↑ before RCLK↑
1.5V
15.5
ns
tsu
Setup time
SRCLR low before RCLK↑
1.5V
10.1
ns
tsu
Setup time
SRCLR high (inactive) before SRCLK↑
1.5V
0.1
ns
th
Hold time
SER after SRCLK↑
1.5V
4
ns
fclock
Clock frequency
1.8V
28
MHz
tw
Pulse duration
RCLK or SRCLK high or low
1.8V
5.5
ns
tw
Pulse duration
SRCLR low
1.8V
4
ns
tsu
Setup time
SER before SRCLK↑
1.8V
3.5
ns
tsu
Setup time
SRCLK↑ before RCLK↑
1.8V
10
ns
tsu
Setup time
SRCLR low before RCLK↑
1.8V
6.7
ns
tsu
Setup time
SRCLR high (inactive) before SRCLK↑
1.8V
0.1
ns
th
Hold time
SER after SRCLK↑
1.8V
2.7
ns
fclock
Clock frequency
2.5V
51
MHz
tw
Pulse duration
RCLK or SRCLK high or low
2.5V
3.8
ns
SN74AC596-Q1
SCASE43 – NOVEMBER 2024
www.ti.com
6
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Copyright © 2024 Texas Instruments Incorporated
Product Folder Links: SN74AC596-Q1



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