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TMP89FS60 Datasheet(PDF) 393 Page - Toshiba Semiconductor |
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TMP89FS60 Datasheet(HTML) 393 Page - Toshiba Semiconductor |
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393 / 410 page ![]() Page 379 TMP89FS60 RA003 25.2.2 MCU mode (Except Flash Programming or erasing) Note:When the supply voltage VDD is less than 3.0V, the operating temperature Topr must be in a range of −20°C to 85 °C. Figure 25-2 Clock gear (fcgck) and High-frequency clock (fc) (VSS = 0 V, Topr = −40 to 85°C) Parameter Symbol Pins Condition Min Max Unit Supply voltage (Condition 1) VDD fc = 8.0 MHz NORMAL1, 2 modes IDLE0, 1, 2 modes 3.0 5.5 V fcgck = 8.0 MHz 4.3 fcgck = 4.2 MHz 3.0 fs = 32.768 kHz SLOW1, 2 modes SLEEP0, 1 modes STOP mode Supply voltage (Condition 2) (Note) fc = 8.0 MHz NORMAL1, 2 modes IDLE0, 1, 2 modes 2.7 3.0 V fcgck = 4.2 MHz fs = 32.768 kHz SLOW1, 2 modes SLEEP0, 1 modes STOP mode Input high level VIH1 MODE pin VDD ≥ 4.5 V VDD × 0.70 VDD V VIH2 Hysteresis input VDD × 0.75 VIH3 VDD < 4.5 V (Note) VDD × 0.90 Input low level VIL1 MODE pin VDD ≥ 4.5 V 0 VDD × 0.30 VIL2 Hysteresis input VDD × 0.25 VIL3 VDD < 4.5 V (Note) VDD × 0.10 Clock frequency fc XIN, XOUT VDD = 2.7 to 3.0 V (Note) 1.0 8.0 MHz VDD = 3.0 to 5.5 V fcgck VDD = 2.7 to 3.0 V (Note) 0.25 4.2 VDD = 3.0 to 4.3 V VDD = 4.3 to 5.5 V 8.0 fs XTIN, XTOUT VDD = 2.7 to 3.0 V (Note) 30.0 34.0 kHz VDD = 3.0 to 5.5 V 5.5 (a) (b) 4.3 2.7 [MHz] Gear clock(fcgck) frequency range [V] 3.0 3.0 5.5 4.3 2.7 [MHz] High-frequency clock(fc) frequency range fc, fc/2 or fc/4 can be used as gear clock (fcgck). Only fc/2 or fc/4 can be used as gear clock (fcgck). Note : The operating temperature Topr range (a) −40°C to 85°C (b) −20°C to 85°C [V] (a) (b) |
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