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TMP89FS60 Datasheet(PDF) 394 Page - Toshiba Semiconductor |
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TMP89FS60 Datasheet(HTML) 394 Page - Toshiba Semiconductor |
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394 / 410 page ![]() Page 380 25. Electrical Characteristics 25.2 Operating Conditions TMP89FS60 RA003 25.2.3 Serial PROM mode Figure 25-3 Clock gear (fcgck) and High-frequency clock (fc) (VSS = 0 V, Topr = −10 to 40°C) Parameter Symbol Pins Condition Min Max Unit Supply voltage VDD NORMAL1, 2 modes 4.5 5.5 V Input high voltage VIH1 MODE pin VDD ≥ 4.5 V VDD × 0.70 VDD VIH2 Hysteresis input VDD × 0.75 Input low voltage VIL1 MODE pin VDD ≥ 4.5 V 0 VDD × 0.30 VIL2 Hysteresis input VDD × 0.25 Clock frequency fc XIN, XOUT VDD ≥ 4.5 V 1.0 8.0 MHz fcgck 0.25 8.0 5.5 4.5 [MHz] Gear clock(fcgck) frequency range [V] 5.5 4.5 [MHz] High-frequency clock(fc) frequency range [V] |
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