TMP89FS60 datasheet(399/410 Pages) TOSHIBA

399 / 410 page

Page 385

TMP89FS60

RA003

Note 6: When the supply voltage VDD is less than 3.0V, the operating temperature Topr must be in a range of

−20°C to 85°C.

25.5 Power-on Reset Circuit Characteristics

Figure 25-6 Power-on Reset Operation Timing

Note: Care must be taken in system designing since the power-on reset circuit may not fulfill its functions due to the fluc-

tuations in the power supply voltage (VDD).

Note 1: Because the power-on reset releasing voltage and the power-on reset detecting voltage change relative to one another,

the detected voltage will never become inverted.

Note 2: A clock output by an oscillating circuit is used as the input clock for a warming-up counter. Because the oscillation fre-

quency does not stabilize until an oscillating circuit stabilizes, some errors may be included in the warming-up time.

Note 3: Boost the power supply voltage such that tVDD becomes smaller that tPWUP.

(VSS=0 V, Topr = −40 to 85°C)

Symbol

Parameter

Min.

Typ.

Max.

Unit

VPROFF

Power-on reset releasing voltageNote

2.2

2.4

2.6

VPRON

Power-on reset detecting voltageNote

2.0

2.2

2.3

tPROFF

Power-on reset releasing response time

−

0.01

0.1

tPRON

Power-on reset detecting response time

−

0.01

0.1

tPRW

Power-on reset minimum pulse width

1.0

−−

tPWUP

Warming-up time after a reset is cleared

−

102 x 29/fc

−

tVDD

Power supply rise time

−−

5ms

Power supply voltage (VDD)

VPROFF

Operating voltage

VPRON

t VDD

tPPW

tPRON

Warm-up counter start

tPWUP

tPROFF

Power-on reset signal

CPU and peripheral circuit

reset signal

Warm-up counter clock

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