TMP89FS60 datasheet(168/410 Pages) TOSHIBA

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Page 154

13. 16-bit Timer Counter (TCA)

13.4 Timer Function

TMP89FS60

RA001

13.4.3 Event counter mode

In the event counter mode, the up counter counts up at the edge of the input to the TCA0 pin.

13.4.3.1 Setting

Setting the operation mode selection TA0MOD<TA0M> to "010" activates the event counter mode.

Set the trigger edge at the external trigger input selection TA0MOD<TA0TED>. Setting

TA0MOD<TA0TED> to "0" selects the rising edge, and setting it to "1" selects the falling edge for count-

ing up.

Note that this mode uses the TA0 input pin, and the TCA0 pin must be set to the input mode beforehand

in port settings.

The operation is started by setting TA0CR<TA0S> to "1". After the timer is started, writing to

TA0MOD and TA0CR<TA0OVE> is disabled. Be sure to complete the required mode settings before

starting the timer.

13.4.3.2 Operation

After the event counter mode is started, when the selected trigger edge is input to the TCA0 pin, the up

counter increments.

When a match between the up counter value and the value set to timer register A (TA0DRA) is detected,

an INTTA0 interrupt request is generated and the up counter is cleared to "0000H". After being cleared,

the up counter continues counting and counts up at each edge of the input to the TCA0 pin. Setting

TA0CR<TA0S> to "0" during the operation causes the up counter to stop counting and be cleared to

"0000H".

The maximum frequency to be supplied is fcgck/2 [Hz] (in the NORMAL 1/2 or IDLE 1/2 mode) or fs/

2 [Hz] (in the SLOW 1/2 or SLEEP 1 mode), and a pulse width of two machine cycles or more is required

TMP89FS60 Datasheet(PDF) 168 Page - Toshiba Semiconductor