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TMPR4951B Datasheet(PDF) 58 Page - Toshiba Semiconductor |
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TMPR4951B Datasheet(HTML) 58 Page - Toshiba Semiconductor |
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58 / 256 page  Chapter 3 TX49/L3 Core’s Registers 3-4 3.2.2 Random register (Reg #1) The Random register is a read only register containing six bits to index an entry in the TLB. This register decrements as each instruction executes. The values are as follows. • A lower bound is set by the number of TLB entries reserved for exclusive use by the operating system (the contents of the Wired register). • An upper bound is set by the total number of TLB entries (47 maximum). The Random register specifies the TLB entry affected by TLB Write Random (TLBWR) instruction. However the register doesn’t need to be read for this purpose, it is readable to verify proper operation of the processor. To simplify testing, the Random register is set to the value of the upper bound upon system reset. This register is also set to the upper bound when the Wired register is written. Figure 3.2.2 shows the format of the Random register and Table 3.2.3 describes the Random register fields. 31 6 5 0 0 Random Figure 3.2.2 Random Register Format Table 3.2.3 Random Register Field Descriptions Bit Field Description Cold Reset Read/Write 31:6 0 Reserved. 0x0 Read 5:0 Random TLB random index for TLBWR instruction. Upper bound (47) Read |
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