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TMPR4951B Datasheet(PDF) 75 Page - Toshiba Semiconductor |
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TMPR4951B Datasheet(HTML) 75 Page - Toshiba Semiconductor |
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75 / 256 page ![]() Chapter 3 TX49/L3 Core’s Registers 3-21 3.2.16 LLAddr Register (Reg #17) The Load Linked Address (LLAddr) register is a read/wirte register, and contains the physical address read by the most recent Load Linked (LL/LLD) instruction. This register is for diagnostic purposes only, and serves no function during normal operation. Figure 3.2.16 shows the format of the LLAddr register and Table 3.2.17 describes the LLAddr register field. 31 0 PAddr[35:4] Figure 3.2.16 LLAddr Register Format Table 3.2.17 LLAddr Register Field Description Bit Field Description Cold Reset Read/Write 31:0 pAddr Physical address bits 35-4 0x0 Read/Write |
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