TMPR4951B datasheet(59/256 Pages) TOSHIBA

59 / 256 page

Chapter 3 TX49/L3 Core’s Registers

3-5

3.2.3

EntryLo0 register (Reg

#2) and EntryLo1 register (Reg#3)

The EntryLo register consists of two registers have identical formats:

•

EntryLo0 is used for even virtual pages

•

EntryLo1 is used for odd virtual pages

The EntryLo0 and EntryLo1 register are read/write register. These registers hold the physical page

frame number (PFN) of the TLB entry for even and odd pages, respectively, when performing TLB read

and write operations.

Figure 3.2.3 shows the format of the EntryLo0/EntryLo1 register and Table 3.2.4 describes the

EntryLo0/EntryLo1 register fields.

32 31

30 29

6 5

3 2

WCE

PFN

Figure 3.2.3 EntryLo0/EntryLo1 Register Format

Table 3.2.4 EntryLo0/EntryLo1 Register Field Descriptions

Bit

Field

Description

Cold Reset

Read/Write

63:32

Reserved

0x0

Read

31:30

WCE

Usable for Win-CE

0x0

Read/Write

29:6

PFN

Page frame number.

Undefined

Read/Write

5:3

Specifies the TLB page coherency attribute.

0: Cacheable, noncoherent, write-through, no-WA

1: Cacheable, noncoherent, write-through, WA

2: Uncached

3: Cacheable,noncoherent,write-back,WA

4-7: Reserved

0x0

Read/Write

Dirty

If this bit is set, the page is marked as dirty and, therefore,

writable. This bit is actually a write-protect bit that software

can use to prevent alteration of data.

Read/Write

Valid

If this bit is set, it indicates that the TLB entry is valid;

otherwise, a TLBL or TLBS miss occurs.

Read/Write

Global

If this bit is set in both EntryLo0 and EntryLo1, then the

processor ignores the ASID during TLB lookup.

Read/Write

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