TMPR4951B datasheet(68/256 Pages) TOSHIBA

68 / 256 page

Chapter 3 TX49/L3 Core’s Registers

3-14

Bit

Field

Description

Cold Reset

Read/Write

Reserved

Read

1: Indicates NMI has occurred.

Read/Write

Reserved

Read

“Hit” or “miss” indication for last CACHE Hit Invalidate, Hit

Write Back Invalidate, Hit Write Back for a primary cache.

0: miss, 1: hit.

Read/Write

17:16

Reserved

0x0

Read

15:8

Interrupt Mask

Controls the enabling of each of the external, internal and

software interrupts. An interrupt is taken if interrupts are

enabled, and the corresponding bits are set in both the IM

field of the Status register and the IP field of the Cause

0: disabled, 0: enabled

0x0

Read/Write

Enables 64-bit addressing in Kernel mode. The extended-

addressing TLB refill exception is used for TLB misses on

kernel addresses.

0: 32-bit, 1: 64-bit

Read/Write

Enables 64-bit addressing and operations in Supervisor

mode. The extended-addressing TLB refill exception is used

for TLB misses on supervisor addresses.

0: 32-bit, 1: 64-bit

Read/Write

Enables 64-bit addressing and operations in User mode. The

extended-addressing TLB refill exception is used for TLB

misses on user addresses.

0: 32-bit, 1: 64-bit

Read/Write

4:3

KSU

Mode.

10: user, 01: supervisor, 00: kernel.

0x0

Read/Write

ERL

Error Level.

0: normal, 1: error.

Read/Write

EXL

Exception Level.

0: normal, 1: exception.

Read/Write

Interrupt Enable.

0: disable, 1: enable.

Read/Write

TMPR4951B Datasheet(PDF) 68 Page - Toshiba Semiconductor

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