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TMPR4951B Datasheet(PDF) 73 Page - Toshiba Semiconductor

Part # TMPR4951B
Description  64-Bit TX System RISC TX49 Family
PDF  256 Pages
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Manufacturer  TOSHIBA [Toshiba Semiconductor]
Direct Link  http://www.semicon.toshiba.co.jp/eng
Logo TOSHIBA - Toshiba Semiconductor

TMPR4951B Datasheet(HTML) 73 Page - Toshiba Semiconductor

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Chapter 3 TX49/L3 Core’s Registers
3-19
3.2.15 Config Register (Reg
#16)
The Config register is a read-only register; except for HALT, ICE#, DCE# and K0 fields. This
register specifies various configuration options selected on the TX49.
EC, BE, IC, DC, IB and DB fields are set by the hardware during reset and are included in this
register as read-only status bits for the software to access. Figure 3.2.15 shows the format of the Config
register and Table 3.2.16 describes the Config register field.
31
30
28 27
24 23
19
18
17
16
15
14
13
12
11
9 8
6
5
4
3
2
0
0
EC
0
0
HALT
ICE
#
DCE
#
BE
1
0
IC
DC
IB
DB
0
K0
Figure 3.2.15 Config Register Format
Table 3.2.16 Config Register Field Descriptions
Bit
Field
Description
Cold Reset
Read/Write
31
0
Reserved
0
Read
30:28
EC
GBUS clock rate:
0: processor clock frequency divided by 2
1: processor clock frequency divided by 3
2: processor clock frequency divided by 4
7: processor clock frequency divided by 2.5
3, 4, 5, 6 : reserved
pin
Read
27:19
0
Reserved
0
Read
18
HALT
Wait mode.
0: Halt
1: Doze
Indicates the power-down behavior of the TX49 when WAIT
instruction is executed. The TX49 stalls the pipeline both in
halt and doze mode.
Cache snoops are possible during
Doze mode but not possible during Halt mode. Halt mode
reduces power consumption to a greater extent than Doze
mode.
0
Read/Write
17
ICE
#
Instruction Cache Enable
0: Instruction cache enable
1: Instruction cache disable
0
Read/Write
16
DCE
#
Data Cache Enable
0: Data cache enable
1: Data cache disable
0
Read/Write
15
BE
Big Endian
0: Little Endian
1: Big Endian
pin
Read
14:13
1
Reserved
11
Read
12
0
Reserved
0
Read



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