TMPR4951B datasheet(89/256 Pages) TOSHIBA

89 / 256 page

Chapter 4 Memory Management System

4-7

4.2.2

Supervisor Mode Operations

Supervisor mode is designed for layered operating systems in which a true kernel runs in Kernel

mode, and the rest of the operating system runs in Supervisor mode.

The processor operates in Supervisor mode when the Status register contains the following bit-values:

•

KSU = 012

•

EXL

= 0

•

ERL

= 0

In conjunction with these bits, the SX bit in the Status register selects between 32- or 64-bit

Supervisor mode addressing:

•

when SX

= 0, 32-bit supervisor space is selected and TLB misses are handled by the 32-bit

TLB refill exception handler

•

when SX

= 1, 64-bit supervisor space is selected and TLB misses are handled by the 64-bit

XTLB refill exception handler

The system maps all references through the TLB, and bit settings within the TLB entry for the page

determine the cacheability of a reference.

Figure 4.2.2 shows Supervisor mode address mapping. Table 4.2.2 lists the characteristics of the

supervisor mode segments; descriptions of the address spaces follow.

0x FFFF FFFF E000 0000

0x 0000 0000 0000 0000

0x 0000 0100 0000 0000

0x 4000 0000 0000 0000

0x 4000 0100 0000 0000

0x FFFF FFFF C000 0000

0x FFFF FFFF FFFF FFFF

xsuseg

xsseg

csseg

suseg

sseg

0x 0000 0000

0x 8000 0000

0x A000 0000

0x C000 0000

0x E000 0000

0x FFFF FFFF

32-bit*

2 GB

Mapped

Cacheable

0.5 GB

Mapped

Cacheable

Address

error

Address

error

Address

error

64-bit

0.5 GB

Mapped

Cacheable

1 TB

Mapped

Cacheable

1 TB

Mapped

Cacheable

Address

error

Address

error

Address

error

Figure 4.2.2 Supervisor Mode Address Space

*Note: In 32-bit mode, bit 31 is sign-extended through bits 63-32.

Failure results in an

address error exception.

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