TMPR4951B datasheet(86/256 Pages) TOSHIBA

86 / 256 page

Chapter 4 Memory Management System

4-4

4.1.5

64-bit Mode Address Translation

Figure 4.1.3 shows the virtual-to-physical-address translation of a 64-bit mode address. This figure

illustrates two of the possible page sizes: a 4-Kbyte page (12 bits) and a 16-Mbyte page (24 bits).

•

The top portion of Figure 4.1.3 shows a virtual address with a 12-bit, or 4-Kbyte, page size,

labelled Offset. The remaining 28 bits of the address represent the VPN, and index the 256M-

entry page table.

•

The bottom portion of Figure 4.1.3 shows a virtual address with a 24-bit, or 16-Mbyte, page

size, labelled Offset. The remaining 16 bits of the address represent the VPN, and index the

64K-entry page table.

Offset passed

unchanged to

physical

memory

Offset passed

unchanged to

physical

memory

Virtual-to-physical

translation in TLB

Bits 62 and 63 of the virtual

address select user, supervisor,

or kernel address spaces.

Virtual-to-physical

translation in TLB

Virtual Address with 64 K (2

16) 16-Mbyte pages

Virtual Address with 256 M (2

28) 4-Kbyte pages

28 bits

= 256M pages

VPN

0 or -1

ASID

Offset

32-bit Physical Address

PFN

Offset

16 bits

= 64 K

VPN

0 or -1

ASID

Offset

TLB

Figure 4.1.3 64-bit Mode Virtual Address Translation

TMPR4951B Datasheet(PDF) 86 Page - Toshiba Semiconductor

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