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TMPR4951B Datasheet(PDF) 74 Page - Toshiba Semiconductor |
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TMPR4951B Datasheet(HTML) 74 Page - Toshiba Semiconductor |
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74 / 256 page ![]() Chapter 3 TX49/L3 Core’s Registers 3-20 Bit Field Description Cold Reset Read/Write 11:9 IC Instruction cache size. In the TX4951B, this is set to 16 KB (010). 010 Read 8:6 DC Data cache size. In the TX4951B, this is set to 8 KB (001). 001 Read 5 IB Primary I-Cache line Size 1: 32 bytes (8 words) 1 Read 4 DB Primary D-cache line Size 1: 32 bytes (8 words) 1 Read 3 0 Reserved 0 Read 2:0 K0 kseg0 coherency algorithm 0: Cacheable, noncoherent, write-through, no-WA 1: Cacheable, noncoherent, write-through, WA 2: Uncached 3: Cacheable, noncoherent, write-back, WA 4-7: Reserved 0x0 Read/Write |
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