TMPR4951B datasheet(69/256 Pages) TOSHIBA

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Chapter 3 TX49/L3 Core’s Registers

3-15

Status Register Modes and Access States

Fields of the Status register set the modes and access states described in the section that follow.

•

Interrupt Enable: Interrupts are enabled when all of the following conditions are met:

•

IE = 1

•

EXL = 0

•

ERL = 0

If these conditions are met, the settings of the IM bits enable the interrupt.

Operation Modes: The following CPU Status register bit settings are required for User, Kernel and

Supervisor modes (see Section 4.2, Operation Modes, for more information about operating

modes).

•

The processor is in User mode when KSU = 102, EXL = 0, and ERL = 0.

•

The processor is in Supervisor mode when KSU = 012, EXL = 0 and ERL = 0.

•

The processor is in Kernel mode when KSU = 002, or EXL= 1, or ERL =1.

32- and 64-bit Modes: The following CPU Status register settings select 32- or 64-bit operation for

User, Kernel, and Supervisor operating modes. Enabling 64-bit operation permits the execution of

64-bit opcodes and translation of 64-bit addresses. 64-bit operation for User, Kernel and

Supervisor modes can be set independently.

•

64-bit addressing for Kernel mode is enabled when KX = 1. 64-bit operations are always

valid in Kernel mode.

•

64-bit addressing and operations are enabled for Supervisor mode when SX = 1.

•

64-bit addressing and operations are enabled for User mode when UX = 1.

Kernel Address Space Accesses: Access to the kernel address space is allowed when the processor

is in Kernel mode.

Supervisor Address Space Accesses: Access to the supervisor address space is allowed when the

processor is in Kernel or Supervisor mode, as described above in the section above titled

Operating Modes.

User Address Space Accesses: Access to the user address is allowed in any of the three operating

modes.

Status Register Reset

The contents of the Status register are undefined at reset, except for the following bits in the

Diagnostic Status field:

•

ERL and BEV = 1

The SR bit distinguishes between the Reset exception and the Soft Reset exception (caused by

Nonmaskable Interrupt [NMI]).

TMPR4951B Datasheet(PDF) 69 Page - Toshiba Semiconductor

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