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TMPR4951B Datasheet(PDF) 119 Page - Toshiba Semiconductor

Part # TMPR4951B
Description  64-Bit TX System RISC TX49 Family
PDF  256 Pages
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Manufacturer  TOSHIBA [Toshiba Semiconductor]
Direct Link  http://www.semicon.toshiba.co.jp/eng
Logo TOSHIBA - Toshiba Semiconductor

TMPR4951B Datasheet(HTML) 119 Page - Toshiba Semiconductor

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Chapter 8 CPU Exception
8-1
8.
CPU Exception
8.1 Introduction
This chapter describes the explanation of CPU exception processing.
The chapter concludes with a
description of each exception’s cause, together with the manner in which the CPU processes and services
these exceptions.
8.2 Exception Vector Locations
Exception vector addresses are stored in an area of kseg0 or kseg1 except for Debug exception vector.
The vector address of the ColdReset, SoftReset and NMI exception is always in a non-cacheable area of
kseg1. Vector addresses of the other exceptions depend on the BEV bit of Status register. When BEV is 0,
these exceptions are vectored to a cacheable area of kseg0. When BEV is 1, all vector addresses are in a
non-cacheable area of kseg1.
Table 8.2.1 shows the list of the exception vector locations.
Table 8.2.1 Exception Vector Locations
Exception
Vector Address (virtual address)
(BEV
= 0)
(BEV
= 1)
ColdReset, NMI
0xffff_ffff_bfc0_0000
0xffff_ffff_bfc0_0000
TLB refill, EXL
= 0
0xffff_ffff_8000_0000
0xffff_ffff_bfc0_0200
XTLB refill, EXL
= 0
(X
= 64-bit TLB)
0xffff_ffff_8000_0080
0xffff_ffff_bfc0_0280
Others (common exception)
0xffff_ffff_8000_0180
0xffff_ffff_bfc0_0380
Exception
Vector Address (physical address)
(BEV
= 0)
(BEV
= 1)
ColdReset, NMI
0x0_1fc0_0000
0x0_1fc0_0000
TLB refill, EXL
= 0
0x0_0000_0000
0x0_1fc0_0200
XTLB refill, EXL
= 0
(X
= 64-bit TLB)
0x0_0000_0080
0x0_1fc0_0280
Others (common exception)
0x0_0000_0180
0x0_1fc0_0380
The cache error exception is not occurred because the TX49 does not have the parity bit into the primary
cache. Debug exception needs the care, it has the special address. Table 8.2.2 shows the list of the debug
exception vector locations.
Table 8.2.2 Debug Exception Vector Locations
Exception
Debug Exception Vector Address (virtual address)
(ProbEnb
= 0)
(ProbEnb
= 1)
Debug
0xffff_ffff_bfc0_0400
0xffff_ffff_ff20_0200
Exception
Debug Exception Vector Address (physical address)
(ProbEnb
= 0)
(ProbEnb
= 1)
Debug
0x0_1fc0_0400
0xf_ff20_0200



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