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Table 5-7. DDRSS2 Signal Descriptions (continued)

SIGNAL NAME [1] ((4)) ((3))

PIN TYPE [2]

DESCRIPTION [3]

ALY PIN [4]

AND PIN [4]

DDR2_DQ12 (1)

DDRSS Data

DDR2_DQ13 (1)

DDRSS Data

DDR2_DQ14 (1)

DDRSS Data

DDR2_DQ15 (1)

DDRSS Data

DDR2_DQ16 (1)

DDRSS Data

DDR2_DQ17 (1)

DDRSS Data

DDR2_DQ18 (1)

DDRSS Data

DDR2_DQ19 (1)

DDRSS Data

DDR2_DQ20 (1)

DDRSS Data

DDR2_DQ21 (1)

DDRSS Data

DDR2_DQ22 (1)

DDRSS Data

DDR2_DQ23 (1)

DDRSS Data

DDR2_DQ24 (1)

DDRSS Data

DDR2_DQ25 (1)

DDRSS Data

DDR2_DQ26 (1)

DDRSS Data

DDR2_DQ27 (1)

DDRSS Data

DDR2_DQ28 (1)

DDRSS Data

DDR2_DQ29 (1)

DDRSS Data

DDR2_DQ30 (1)

DDRSS Data

DDR2_DQ31 (1)

DDRSS Data

DDR2_DQS0N (1)

DDRS Complimentary Data Strobe

DDR2_DQS0P (1)

DDRS Data Strobe

DDR2_DQS1N (1)

DDRS Complimentary Data Strobe

DDR2_DQS1P (1)

DDRS Data Strobe

DDR2_DQS2N (1)

DDRS Complimentary Data Strobe

DDR2_DQS2P (1)

DDRS Data Strobe

DDR2_DQS3N (1)

DDRS Complimentary Data Strobe

DDR2_DQS3P (1)

DDRS Data Strobe

(1)

This signal is not supported on AM69A94, AM6954 devices. Please refer to Device Comparison and Pin Attributes table for the

complete list of supported IP and signals.

(2)

An external 240 Ω ±1% resistor must be connected between this pin and VSS. No external voltage should be applied to this pin.

(3)

DDRSS0, DDRSS1, DDRSS2, and DDRSS3 must always be used in incremental order. For instance, when using a single LPDDR

component, it must be connected to the DDR0_* interface. When using two LPDDR components, they must be connected to DDR0_*

and DDR1_* interfaces, and so forth.

(4)

DDRSS2, DDRSS3, and SERDES2 are not available on the 27mm package variant of this SoC. DDRSS2/DDRSS3/SERDES2 should

be avoided if software compatibility is desired with systems that use the 27mm package.

Table 5-8. DDRSS3 Signal Descriptions

SIGNAL NAME [1] ((4)) ((3))

PIN TYPE [2]

DESCRIPTION [3]

ALY PIN [4]

AND PIN [4]

DDR3_CKN (1)

DDRSS Differential Clock (negative)

B25

DDR3_CKP (1)

DDRSS Differential Clock (positive)

A24

DDR3_RESETn (1)

DDRSS Reset

C23

DDR3_RET (1)

DDR Retention Enable

G27

DDR3_CA0 (1)

DDRSS Command Address

D25

DDR3_CA1 (1)

DDRSS Command Address

B23

DDR3_CA2 (1)

DDRSS Command Address

D24

DDR3_CA3 (1)

DDRSS Command Address

C24

DDR3_CA4 (1)

DDRSS Command Address

E23

AM69A, AM69

SPRSP92D – FEBRUARY 2023 – REVISED DECEMBER 2024

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