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TMP88CS38 Datasheet(PDF) 123 Page - Toshiba Semiconductor |
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TMP88CS38 Datasheet(HTML) 123 Page - Toshiba Semiconductor |
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123 / 226 page  TMP88CS38/CM38A/CP38A 2007-09-12 88CS38-123 AD Conversion Result Register 7 6 5 4 3 2 1 0 ADCDR1 (00031H) AD07 AD06 AD05 AD04 AD03 AD02 AD01 AD00 (Initial value: 0000 0000) 7 6 5 4 3 2 1 0 ADCDR2 (00032H) − − EOCF ADBF − − − − (Initial value: **00 ****) EOCF AD conversion end flag 0: Under conversion or before conversion 1: End of conversion ADBF AD conveersion busy flag 0: During stop of AD conversion 1: During AD conversion Read only Note 1: The EOCF is cleared to “0” when reading the ADCDR1. Therefore, the AD conversion result should be read to ADCDR1 more first than ADCDR2. Note 2: ADBR is set to “1” by starting AD conversion and cleared to “0” by end of AD conversion. Additionally, ADBF is cleared to “0” by setting AMD = “00” in ADCCR2 or entering to the STOP mode. Figure 2.11.3 AD Converter Result Register 2.11.3 AD Converter Operation The high side of an analog reference voltage is applied to VDD, and the low side is applied to VSS pin. Dividing a reference voltage between VDD and VSS to the voltage corresponding to a bit by a rudder resistance and comparing it with the analog input voltage converts the AD. Table 2.11.1 AD Converter Operation Mode Mode Function AD converter disable mode AD converter stop mode. This mode is always used to change modes. Software start mode Single AD conversion of 1 channel which specifies input. Trigger start mode Single AD conversion of 1 channel which specifies input (AD8TRG) from Key-on wakeup circuit as a trigger. 2.11.4 Interrupt Interrupt request signal occur at the timing when the EOCF bit is set to “1”. |
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