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TMP88CS38 Datasheet(PDF) 141 Page - Toshiba Semiconductor |
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TMP88CS38 Datasheet(HTML) 141 Page - Toshiba Semiconductor |
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141 / 226 page  TMP88CS38/CM38A/CP38A 2007-09-12 88CS38-141 2.14.2 Control The test video signal output circuit can be controlled with the test video signal control register. 7 6 5 4 3 2 1 0 TVSCR (00FE6H) SGEN SGVBLK SGPAL SGIV SGCHS “0” SGPAT “0” (Initial value: 0000 0000) SGEN SG function selection 0: Disable 1: Enable SGVBLK Picuture signal for VBLK duration time 0: Output 1: No output SGPAL PAL/NTSC selection 0: NTSC 1: PAL SGIV Pattern monochromatic inversion 0: No inversion 1: Inversion SGCHS OSD synchronous signal selection 0: Port 1: Pseudo signal circuit SGPAT Display pattern 000:Black on the whole screen 001:White on the whole screen 010:Cross hatch 011:Cross dot pattern 100:Cross bar 101:White on the upper side/black on the lower side 110:H signal pattern 111:H resolution pattern Write only Note 1: Test video signal output function does work correctly when fc is not 16 MHz. Note 2: Clear the bit2 and bit0 of TVSCR to “0”. Figure 2.14.2 Test Video Signal Control Register |
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