TMP88CS38 datasheet(186/226 Pages) TOSHIBA

186 / 226 page

TMP88CS38/CM38A/CP38A

2007-09-12

88CS38-186

2.15.5.8.1 Operating Principle

The clock generator for OSD display consists of a ring oscillator, an 11-bit counter,

a comparator and an oscillator controller. The frequency of the ring oscillator

depends on the cycle of the external HD input and the ORCLKC setting. The ring

oscillator generates clocks required for one scanning line and the 11-bit counter

counts the number of clocks. Then the counted number of the upper-order 8 bits is

compared with the value set by ORCLCK. The comparator sends the compared

result, which controls the ring oscillator and changes the oscillating frequency. At

the frequencies of 8 MHz, 16 MHz and 24 MHz set by ORCLKC, the error

percentages are 1.65%, 0.83% and 0.55% respectively. Thus, even when the same

value is rewritten to ORCLKC, the display position after refresh deviates by the

error percentage (Note 1).

The oscillator controller controls the operation of the ring oscillator using a result

from the comparator. To avoid display jitter created by fine adjustment, the oscillator

controller receives a coincidence signal and automatically stops adjusting the ring

oscillator. After the ring oscillator becomes stable, it drives a display clock at a

regular frequency. The output frequency fluctuates according to changes of

temperature and voltage (Note 2). The frequency of the ring oscillator can be

adjusted to the required frequency (Display position) by writing value to ORCLKC in

response to the change of condition.

When the oscillating frequency of the ring oscillator is adjusted under software

control, please writes value before adjustment to ORCLKC.The comparator

compares ORCLKF (the result from comparing the counted number of the

upper-order 8 bits of the 11-bit counter with the ORCLKC setting value.) with the

ORCLKC setting value.

Comparing ORCLKF with ORCLKC, the deviation of the oscillating frequency is

checked and please writes values before adjustment to ORCLKC.

In this case, the deviation of the display position occurs as described in Note 1.

Therefore, care must be taken to the interval of adjusting the frequency of the ring

oscillator.

Note 1: Since the clock generator for OSD display controls the frequency using the

upper-order 8 bits of the 11-bit counter, the low-order 3 bits do not participate in

determining the frequency. This yields an error equal to relative magnitude of the

low-order 3 bits at maximum. Even when the same value is set to a register, up to

8-count error occurs in one line. (Errors when using clock generator for OSD

display in NTSC (interlace) mode (HD

= 53.2 μs) are explained subsequently.)

TMP88CS38 Datasheet(PDF) 186 Page - Toshiba Semiconductor