IR35211 datasheet(28/58 Pages) IRF

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Dual Output Digital Multi-Phase Controller

IR35211

July 24, 2014 | V1.00

Note the Vmax register must be set appropriately to

allow the required output voltage offset.

Intel Reporting Offsets

In addition to the mandatory features of the SVID bus,

the IR35211 provides optional volatile SVID registers

which allow the user to offset the reporting on the

SVID interface as detailed in Table 22.

TABLE 22: SVID OFFSET REGISTERS

Parameter

Memory

Range

Step size

Output Current

NVM

-4A to +3.75A

0.25A

Temperature

R/W

-32°C to +31°C

1°C

VR12.5 Operation

VR12.5 mode is selectable via either a MTP bit or

external pin (INMODE) pulled low. The boot voltage in

VR12.5 is also selectable and can be taken from

either the boot registers (Table 27) or from 4 fixed VID

values (Table 23).

TABLE 23: VR12.5 BOOT VOLTAGES

1.65V

1.7V

1.75V

Memory (MPoL) Mode

In MPoL mode the IR35211 configures Loop 2 VID to

50% of Loop 1. Communication with and control of the

IR35211 may occur either through the SVID interface

where an Intel SVID Master is present or alternatively

through the I2C/SMBus/PMBus interface for non-Intel

applications.

The IR35211 follows startup and timing requirements

as shown in Figure 18 and Table 24. When the power-

on sequence is initiated, and with VBOOT set to > 0V,

both rails will ramp to their configured voltages and

assert VR_READY_L1 and VR_READY_L2. The slew

rates for both loops are set independently per Table 3.

If tracking is required during the slew, then care must

be taken to ensure that the Loop 2 slew rate is set to

½ of the Loop 1 slew rate. Typical MPoL start-up and

shut-down waveforms are shown in Figure 19 and

Figure 20.

Figure 18: MPoL Startup

TABLE 24: MPOL START-UP TIMING

Time

Description

Min

Typ

Max

VR_EN to Loop 1 start

3µs

Loop 2 delay

Table

Voltage ramp complete to

VR_RDY_L1/L2

1µs

Figure 19: MPoL Tracking Startup

Figure 20: MPoL Tracking Shutdown

In MPoL mode, Loop 2 start-up can be delayed

relative to Loop 1 according to Table 25.

TABLE 25: MPOL LOOP 2 START-UP DELAY

Loop 2 Delay

0 – 678.3usec in 2.66usec Steps

Vout 1

Vout 2

Vout 1

Vout 2

IR35211 Datasheet(PDF) 28 Page - International Rectifier

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