IR35211 datasheet(13/58 Pages) IRF

13 / 58 page

Dual Output Digital Multi-Phase Controller

IR35211

July 24, 2014 | V1.00

Figure 4: Persistence plot of a 3Φ, 50A system

Figure 5: Persistence plot in 1Φ, 10A

HIGH-PRECISION VOLTAGE REFERENCE

The internal high-precision voltage reference supplies

the required reference voltages to the VID DACs,

ADCs and other analog circuits. This factory trimmed

reference is guaranteed over temperature and

manufacturing variations.

HIGH PRECISION CURRENT REFERENCE

An on-chip precision current reference is derived

using an off-chip precision resistor connected to the

RRES pin of the IR35211. RRES must be a 7.5kΩ,

1% tolerance resistor, placed very close to the

controller pin to minimize parasitics.

VOLTAGE SENSE

An error voltage is generated from the difference

between the target voltage, defined by the VID and

load line (if implemented), and the differential,

remotely sensed, output voltage. For each loop, the

error voltage is digitized by a high-speed, high-

precision ADC. An anti-alias filter provides the

necessary high frequency noise rejection. The gain

and offset of the voltage sense circuitry for each loop

is factory trimmed to deliver the required accuracy.

CURRENT SENSE

Lossless inductor DCR or precision resistor current

sensing is used to accurately measure individual

phase currents. Using a simple off-chip thermistor,

resistor and capacitor network for each loop, a

thermally compensated load line is generated to meet

the given power system requirement. A filtered

voltage, which is a function of the total load current

and the target load line resistance, is summed into

each voltage sense path to accomplish the Active

Voltage Positioning (AVP) function.

VID DECODER

The VID decoder receives a VID code from the CPU

that is converted to an internal code representing the

VID voltage. This block also outputs the signal for VR

disable if a VID shutdown code has been received.

The VID code is 8 bits in AMD SVI2 & Intel

VR12/VR12.5 mode and 7 bits in AMD SVI1 mode.

MOSFET DRIVER, POWER STAGE AND

DRMOS COMPATIBILITY

The output PWM signals of the IR35211 are designed

for compatibility with the CHL85xx family of active tri-

level (ATL) MOSFET drivers. CHL85xx drivers have a

fast disable capability which enables any phase to be

turned off on-the-fly. It supports power-saving control

modes, improved transient response, and superior on

the fly phase dropping without having to route multiple

output disable (ODB or SMOD) signals.

In addition, the IR35211 provides the flexibility to

configure PWM levels to operate with external

MOSFET drivers, Power Stages or driver-MOSFET

(DrMOS) devices that support Industry standard

+3.3V tri-state signaling.

I2C & PMBUS INTERFACE

An I2C or PMBus interface is used to communicate

with the IR35211. This two-wire serial interface

consists of clock and data signals and operates as

fast as 1MHz. The bus provides read and write access

to the internal registers for configuration and

monitoring of operating parameters and can also be

used to program on-chip non-volatile memory (MTP)

to store operating parameters.

PWM1

PWM2

PWM3

Vdd

IR35211 Datasheet(PDF) 13 Page - International Rectifier

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