IR35211 datasheet(39/58 Pages) IRF

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Dual Output Digital Multi-Phase Controller

IR35211

July 24, 2014 | V1.00

During a load transient overshoot, the ATA can also

be programmed to turn off the low-side MOSFETS

instead of holding them on. This forces the load

current to flow through the larger forward voltage of

the FET body diode and helps to reduce the

overshoot created during a load release (Figure 34).

Figure 34: Diode Emulation during a load release

HIGH-SPEED PHASE BALANCE

The IR35211 provides phase balance during high

frequency load oscillations. The balance is provided

through phase skipping. Whenever a set error voltage

threshold, load oscillation frequency threshold, and a

pulse width delta threshold is exceeded for a

particular phase, that phase is skipped resulting in a

lowering of current in the skipped phase and a

corresponding increase in current in the other phases.

All three thresholds in Table 33 are user

programmable to provide flexibility in high-speed

phase balance for a wide variety of systems.

TABLE 33: HIGH-SPEED THRESHOLDS

Function

Hspb_delta

Pulse width delta threshold. Difference between

the average of a particular phase pulse width

and the average of all other phase pulse widths.

Phase is skipped when its pulse width delta

exceeds the threshold.

Disable HSPB, 40nsec – 600nsec, 40nsec

resolution.

Hspb_hth

Error Voltage threshold.

Activates HSPB when the threshold is

exceeded.

0mV – 60mV, 4mV resolution

Hspb_fth

Load Oscillation Frequency Threshold.

Activates HSPB when the load oscillation

frequency is above threshold.

0kHz – 703.5kHz, 46.9kHz resolution.

DYNAMIC VID SLEW RATE

The IR35211 provides the VR designer with 4 slew

rates in AMD SVI2 mode up to 25mV/us (Fast rate

only) and up to 12 slew rates in Intel mode by

selecting a slew rate setting as shown in Table 34.

These slew rates can be further reduced by 10x by a

TABLE 34: SLEW RATES

mV/µs

FAST rate

½ Multiplier

¼ Multiplier

5.0

2.50

7.5

3.75

5.00

12.5

6.25

DYNAMIC VID COMPENSATION

The IR35211 can compensate for the error produced

by the current feedback in a system with AVP (Active

Voltage Positioning) when the output voltage is

ramping to a higher voltage. MTP parameters are

provided that set an output capacitance term and an

AVP bandwidth term such that the user can model the

effects that the inrush current into the output bulk

capacitors has on the error voltage and thus the

output voltage when the voltage is ramping to a higher

voltage. Once properly modeled the output voltage will

more closely follow the DAC during a positive dynamic

VID and provide better dynamic VID alert timing

required by Intel

® and AMD® processors. Figure 35

shows the effects that Dynamic VID Compensation

has on the output voltage and the alert timing.

Figure 35: Dynamic VID Compensation

Diode Emulation:

Disabled

Enabled

No DVID Compensation

DVID Compensation set to model

~7500uF of output capacitance

IR35211 Datasheet(PDF) 39 Page - International Rectifier

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