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Document number: BST-BME280-DS001-23 Revision_1.23_012022

6.3.2

SPI read

Reading is done by lowering CSB and first sending one control byte. The control bytes consist of the

SPI register address (= full register address without bit 7) and the read command (bit 7 = RW = ‘1’).

After writing the control byte, data is sent out of the SDO pin (SDI in 3-wire mode); the register address

is automatically incremented. The SPI read protocol is depicted in Figure 13.

Start RW

Stop

0 bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0

CSB

Data byte

Data register - address F7h

CSB

Control byte

Data byte

Data register - address F6h

Figure 13: SPI multiple byte read

6.4 Interface parameter specification

6.4.1

General interface parameters

The general interface parameters are given in Table 32 below.

Table 32: interface parameters

Parameter

Symbol

Condition

Min

Typ

Max

Unit

Input low level

Vil_si

VDDIO=1.2 V to 3. 6V

%VDDI

Input high level

Vih_si

VDDIO=1.2 V to 3.6 V

%VDDI

Output low level I2C

Vol_SDI

VDDIO=1.62 V, Iol=3 mA

%VDDI

Output low level I2C

Vol_SDI_1.2

VDDIO=1.20 V, Iol=3 mA

%VDDI

Output low level SPI

Vol_SDO

VDDIO=1.62 V, Iol=1 mA

%VDDI

Output low level SPI

Vol_SDO_1.2

VDDIO=1.20 V, Iol=1 mA

%VDDI

Output high level

Voh

VDDIO=1.62 V, Ioh=1 mA

(SDO, SDI)

%VDDI

Output high level

Voh_1.2

VDDIO=1.20 V, Ioh=1 mA

(SDO, SDI)

%VDDI

Pull-up resistor

Rpull

Internal CSB pull-up

resistance to VDDIO

120

190

kΩ

I2C bus load capacitor

On SDI and SCK

400

6.4.2

I²C timings

For I²C timings, the following abbreviations are used:

•

“S&F mode” = standard and fast mode

•

“HS mode” = high speed mode

•

Cb = bus capacitance on SDA line

All other naming refers to I²C specification 2.1 (January 2000).

The I²C timing diagram is in Figure 14. The corresponding values are given in Table 33.

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