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AX88772 Datasheet(PDF) 28 Page - ASIX Electronics Corporation

Part # AX88772
Description  USB to 10/100 Fast Ethernet/HomePNA Controller
PDF  43 Pages
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Manufacturer  ASIX [ASIX Electronics Corporation]
Direct Link  http://www.asix.com.tw
Logo ASIX - ASIX Electronics Corporation

AX88772 Datasheet(HTML) 28 Page - ASIX Electronics Corporation

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ASIX ELECTRONICS CORPORATION
28
AX88772
USB to 10/100 Fast Ethernet/HomePNA Controller
6.2.2
Remote Wakeup Description
After AX88772 enters into suspend mode, either the USB host or AX88772 itself can awake it up and resume back to the
original operation mode before it entered suspend. Following truth table shows the chip setting, wakeup event, and device
response supported by this ASIC. Note that “X” stands for don’t-care.
Setting
Wakeup Event
Device
awakes up?
Wakeup
by
RWU bit
of Flag
byte in
EEPRO
M
Set_Feature
standard
command
RWLU of
Monitor
Mode
Register
RWMP of
Monitor
Mode
register
Host send
resume
signal
Receiving
Magic
Packet
EXTWAKE
UP_N pin
Linkup
detected
on
Primary
Phy
Linkup
detected on
Secondary
Phy
Host
X
X
X
X
J -> K
Yes
Device
0
0
X
X
X
X
X
X
No
Device
1
1
0
1
Yes
Yes
Device
1
1
1
0
Yes
Yes
Device
1
1
1
0
Yes
Yes
Device
1
1
X
X
Low-pulse
Yes
Table 5: Remote Wakeup Truth Table
6.3 Interrupt Endpoint
The Interrupt Endpoint contains 8 bytes of data and its frame format is defined as: A100_BB00_CCDD_EEFF.
Where BB byte in byte 3:
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
Reserved
MDINT
FLE
SPLS
PPLS
PPLS: Primarily PHY Link State.
1: Link is up.
0: Link is down.
SPLS: Secondary PHY Link State.
1: Link is up.
0: Link is down.
FLE: Bulk Out Ethernet Frame Length Error.
1: Proprietary Length field has parity error during Bulk Out transaction.
0: Proprietary Length field has no parity error during Bulk Out transaction.
MDINT: Input level of MDINT pin. The MDINT pin can be connected to MDINT# pin of Ethernet Phy.
1: When MDINT input pin = 1.
0: When MDINT input pin = 0.
CCDD byte in byte 5 and 6: Primary Phy’s register value, whose offset is given in High byte of EEPROM offset 0Fh.
EEFF byte in byte 7 and 8: Primary Phy’s register value, whose offset is given in Low byte of EEPROM offset 0Fh.



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