PCM1870 datasheet(13/52 Pages) TI2

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DESCRIPTION OF OPERATION

System Clock Input

w(SCKH)

SCKI

w(SCKL)

0.7V

0.3V

T0005-12

Power-On Reset and System Reset

Power On/Off Sequence

PCM1870

SLAS544A – MAY 2007 – REVISED SEPTEMBER 2007

The PCM1870 can accept input clocks of various frequencies without a PLL. The clocks are used for clocking of

the digital filters, auto level control, and delta-sigma modulators, and classified into common-audio and

application-specific clocks. Table 2 shows frequencies of the common audio clock and the application-specific

clock. Figure 13 shows timing requirements for system clock inputs. The sampling rate and frequency of the

system clock are determined by settings in register 86 (MSR[2:0]) and register 85 (NPR[5:0]). Note that the

sampling rate of the application-specific clock has a little sampling error. The details are shown in Table 8.

Table 2. Frequency of Common Audio Clock

FREQUENCY

Common audio clock

11.2896, 12.288, 16.9344, 18.432 MHz

Application-specific clock

12, 13, 13.5, 24, 26, 27, 19.2, 19.68, 38.4, 39.36 MHz

PARAMETERS

SYMBOL

MIN

UNIT

System clock pulse duration, high

tw(SCKH)

System clock pulse duration, low

tw(SCKL)

Figure 13. System Clock Timing

The power-on-reset circuit outputs reset signal, typically at VDD = 1.2 V, and this circuit does not depend on the

voltage of other power-supplies (VCC, VPA, and VIO). Internal circuits are cleared to default status, then signals

are removed from all analog and digital outputs. The PCM1870 does not require any power supply sequencing.

System reset is enabled by setting register 85 (SRST), and all registers are cleared automatically. All circuits are

reset to their default status at once. Note that the PCM1870 has audible pop noise on the analog outputs when

enabling SRST.

To reduce audible pop noise, a sequence of register settings is required after turning all power supplies on when

powering up, or before turning the power supplies off when powering down. If some modules are not required for

a particular application or operation, they should be placed in the power-down state after performing the

power-on sequence. The recommended power-on and power-off sequences are shown in Table 3 and Table 4,

respectively.

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