PCF85263ATLSLASHA datasheet(28/100 Pages) NXP

28 / 100 page

PCF85263A

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Product data sheet

Rev. 4.1 — 27 November 2015

28 of 100

NXP Semiconductors

PCF85263A

Tiny RTC with alarm, battery switch-over, and I2C-bus

8.5.1.3

WatchDog interrupts

The generation of interrupts from the WatchDog functions is controlled via the WatchDog

interrupt enable bits; WDIEA and WDIEB. These bits are in registers INTA_enable

(address 29h) and INTB_enable (address 2Ah).

The assertion of the flag WDF can be used to generate an interrupt at pins INTA and

INTB. The interrupt may be generated as a pulsed signal every time the WatchDog

counter reaches the end of the countdown period. Alternatively as a permanently active

signal which follows the condition of bit WDF. WDF remains set until cleared by command.

When enabled, interrupts are triggered every time the WatchDog counter reaches the end

of the countdown period and even if the WDF is not cleared, an interrupt pulse can be

generated.

See Section 8.9 on page 38 for interrupt control.

8.6 RAM byte

[1]

Default value.

The PCF85263A provides a free RAM byte, which can be used for any purpose, for

example, status bits of the system.

8.7 Timestamps

There are three timestamp registers which can be independently configured to record the

time for battery switch-over events and/or transitions on the TS pin.

Each timestamp register has an associated flag. It is also possible to generate an interrupt

signal for every timestamp register update.

Fig 15. WatchDog single shot mode

Table 19.

RAM_byte - 8-bit RAM register (address 2Ch) bit description

Bit

Symbol

Value

Description

7 to 0

B[7:0]

00000000[1] to

11111111

RAM content

PCF85263ATL/A Datasheet(PDF) 28 Page - NXP Semiconductors

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