PCF85263ATLSLASHA datasheet(56/100 Pages) NXP

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PCF85263A

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Product data sheet

Rev. 4.1 — 27 November 2015

56 of 100

NXP Semiconductors

PCF85263A

Tiny RTC with alarm, battery switch-over, and I2C-bus

8.13.5 COF[2:0]: Clock output frequency

[1]

Default value.

A programmable square wave is available at pin CLK. Operation is controlled by the

COF[2:0] bits. Frequencies of 32.768 kHz (default) down to 1 Hz can be generated for use

as a system clock, microcontroller clock, input to a charge pump, or for calibration of the

oscillator.

Pin CLK is a push-pull output and enabled at power-on. Pin CLK can be disabled by

setting CLKPM = 1 in the Pin_IO register (Section 8.12 on page 50). When disabled, the

CLK pin is LOW.

The selected clock frequency may also be output on the TS pin and the INTA pin. The

CLKIV bit may be used to invert the clock output. CLKIV does not invert for the setting

COF[2:0] = 111.

The duty cycle of the selected clock is not controlled. However, due to the nature of the

clock generation, all clock frequencies except 32.768 kHz have a duty cycle of 50 : 50.

[1]

Duty cycle definition: % HIGH-level time : % LOW-level time.

[2]

Default values. The duty cycle of the CLKOUT when outputting 32,768 Hz could change from 60:40 to

40:60 depending on the detector since the 32,768 Hz is derived from the oscillator output which is not

perfect. It could change from device to device and it depends on the silicon diffusion. There is nothing that

can be done from outside the chip to influence the duty cycle.

[3]

1 Hz clock pulses are not affected by offset correction pulses.

Table 58.

COF[2:0] bits - Function control register (address 28h)

Bit

Symbol

Value

Frequency selection (Hz)

CLK pin

TS pin

INTA pin

2 to 0

COF[2:0]

000[1]

32768

001

16384

010

8192

011

4096

100

2048

101

1024

110

111

static LOW

Hi-Z

Table 59.

Clock duty cycles

COF[2:0]

Frequency (Hz)

Typical duty cycle[1]

000[2]

32768

60 : 40 to 40 : 60

001

16384

50 : 50

010

8192

50 : 50

011

4096

50 : 50

100

2048

50 : 50

101

1024

50 : 50

110

1[3]

50 : 50

111

static

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